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afddfeaf4a
Do not break down local loads and stores so ds_read/write_b96/b128 in ISelLowering can be selected on subtargets that support them and if align requirements allow them. Differential Revision: https://reviews.llvm.org/D84403
152 lines
4.2 KiB
LLVM
152 lines
4.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
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; Testing for ds_read/write_128
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; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=SI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
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; FUNC-LABEL: {{^}}load_f32_local:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b32
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; EG: LDS_READ_RET
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define amdgpu_kernel void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) #0 {
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entry:
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%tmp0 = load float, float addrspace(3)* %in
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store float %tmp0, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v2f32_local:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) #0 {
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entry:
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%tmp0 = load <2 x float>, <2 x float> addrspace(3)* %in
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store <2 x float> %tmp0, <2 x float> addrspace(1)* %out
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ret void
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}
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; FIXME: should this do a read2_b64?
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; FUNC-LABEL: {{^}}local_load_v3f32:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8
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; SI-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}}
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; CIVI-DAG: ds_read_b96 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}}
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; GCN: s_waitcnt
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; SI-DAG: ds_write_b64
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; SI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8{{$}}
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; CIVI-DAG: ds_write_b96 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v3f32(<3 x float> addrspace(3)* %out, <3 x float> addrspace(3)* %in) #0 {
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entry:
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%tmp0 = load <3 x float>, <3 x float> addrspace(3)* %in
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store <3 x float> %tmp0, <3 x float> addrspace(3)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v4f32:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v4f32(<4 x float> addrspace(3)* %out, <4 x float> addrspace(3)* %in) #0 {
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entry:
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%tmp0 = load <4 x float>, <4 x float> addrspace(3)* %in
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store <4 x float> %tmp0, <4 x float> addrspace(3)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v8f32:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v8f32(<8 x float> addrspace(3)* %out, <8 x float> addrspace(3)* %in) #0 {
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entry:
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%tmp0 = load <8 x float>, <8 x float> addrspace(3)* %in
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store <8 x float> %tmp0, <8 x float> addrspace(3)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_load_v16f32:
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; SICIVI: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; GCN: ds_read2_b64
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_load_v16f32(<16 x float> addrspace(3)* %out, <16 x float> addrspace(3)* %in) #0 {
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entry:
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%tmp0 = load <16 x float>, <16 x float> addrspace(3)* %in
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store <16 x float> %tmp0, <16 x float> addrspace(3)* %out
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ret void
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}
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; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
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; FUNC-LABEL: {{^}}local_v4f32_to_128:
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; SI-NOT: ds_read_b128
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; SI-NOT: ds_write_b128
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; CIVI: ds_read_b128
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; CIVI: ds_write_b128
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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; EG: LDS_READ_RET
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define amdgpu_kernel void @local_v4f32_to_128(<4 x float> addrspace(3)* %out, <4 x float> addrspace(3)* %in) {
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%ld = load <4 x float>, <4 x float> addrspace(3)* %in, align 16
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store <4 x float> %ld, <4 x float> addrspace(3)* %out, align 16
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ret void
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}
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attributes #0 = { nounwind }
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