1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
llvm-mirror/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
Matt Arsenault cc12b285b6 CodeGen: Print/parse LLTs in MachineMemOperands
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00

63 lines
1.8 KiB
YAML

# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
# Check that SILoadStoreOptimizer honors physregs defs/uses between moved
# instructions.
#
# The following IR snippet would usually be optimized by the peephole optimizer.
# However, an equivalent situation can occur with buffer instructions as well.
# CHECK-LABEL: name: scc_def_and_use_no_dependency
# CHECK: S_ADD_U32
# CHECK: S_ADDC_U32
# CHECK: DS_READ2_B32
---
name: scc_def_and_use_no_dependency
machineFunctionInfo:
isEntryFunction: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
%1:vgpr_32 = COPY $vgpr0
%10:sgpr_32 = COPY $sgpr0
$m0 = S_MOV_B32 -1
%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32))
%11:sgpr_32 = S_ADD_U32 %10, 4, implicit-def $scc
%12:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
%3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load (s32))
S_ENDPGM 0
...
# CHECK-LABEL: name: scc_def_and_use_dependency
# CHECK: DS_READ2_B32
# CHECK: S_ADD_U32
# CHECK: S_ADDC_U32
---
name: scc_def_and_use_dependency
machineFunctionInfo:
isEntryFunction: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
%1:vgpr_32 = COPY $vgpr0
%10:sgpr_32 = COPY $sgpr0
$m0 = S_MOV_B32 -1
%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load (s32))
%20:sgpr_32 = V_READFIRSTLANE_B32 %2, implicit $exec
%21:sgpr_32 = S_ADD_U32 %20, 4, implicit-def $scc
; The S_ADDC_U32 depends on the first DS_READ_B32 only via SCC
%11:sgpr_32 = S_ADDC_U32 %10, 0, implicit-def dead $scc, implicit $scc
%3:vgpr_32 = DS_READ_B32 %1, 64, 0, implicit $m0, implicit $exec :: (load (s32))
S_ENDPGM 0
...