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d1f23a1772
Support for XNACK and SRAMECC is not static on some GPUs. We must be able to differentiate between different scenarios for these dynamic subtarget features. The possible settings are: - Unsupported: The GPU has no support for XNACK/SRAMECC. - Any: Preference is unspecified. Use conservative settings that can run anywhere. - Off: Request support for XNACK/SRAMECC Off - On: Request support for XNACK/SRAMECC On GCNSubtarget will track the four options based on the following criteria. If the subtarget does not support XNACK/SRAMECC we say the setting is "Unsupported". If no subtarget features for XNACK/SRAMECC are requested we must support "Any" mode. If the subtarget features XNACK/SRAMECC exist in the feature string when initializing the subtarget, the settings are "On/Off". The defaults are updated to be conservatively correct, meaning if no setting for XNACK or SRAMECC is explicitly requested, defaults will be used which generate code that can be run anywhere. This corresponds to the "Any" setting. Differential Revision: https://reviews.llvm.org/D85882
130 lines
5.2 KiB
LLVM
130 lines
5.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: reassoc_i32:
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; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD1]], v{{[0-9]+}}
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[ADD1]], v{{[0-9]+}}
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define amdgpu_kernel void @reassoc_i32(i32 addrspace(1)* %arg, i32 %x, i32 %y) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add1 = add i32 %x, %tid
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%add2 = add i32 %add1, %y
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store i32 %add2, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: reassoc_i32_swap_arg_order:
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; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD1]], v{{[0-9]+}}
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[ADD1]], v{{[0-9]+}}
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define amdgpu_kernel void @reassoc_i32_swap_arg_order(i32 addrspace(1)* %arg, i32 %x, i32 %y) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add1 = add i32 %tid, %x
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%add2 = add i32 %y, %add1
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store i32 %add2, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: reassoc_i64:
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; GCN: s_add_u32 [[ADD1L:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: s_addc_u32 [[ADD1H:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GFX8-DAG: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD1L]], v{{[0-9]+}}
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; GFX9-DAG: v_add_co_u32_e32 v{{[0-9]+}}, vcc, [[ADD1L]], v{{[0-9]+}}
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; GCN-DAG: v_mov_b32_e32 [[VADD1H:v[0-9]+]], [[ADD1H]]
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; GFX8: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, [[VADD1H]], vcc
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, [[VADD1H]], vcc
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define amdgpu_kernel void @reassoc_i64(i64 addrspace(1)* %arg, i64 %x, i64 %y) {
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bb:
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%tid32 = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tid = zext i32 %tid32 to i64
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%add1 = add i64 %x, %tid
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%add2 = add i64 %add1, %y
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store i64 %add2, i64 addrspace(1)* %arg, align 8
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ret void
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}
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; GCN-LABEL: reassoc_v2i32:
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; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: s_add_i32 [[ADD2:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GFX8-DAG: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD1]], v{{[0-9]+}}
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; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD2]], v{{[0-9]+}}
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; GFX9-DAG: v_add_u32_e32 v{{[0-9]+}}, [[ADD1]], v{{[0-9]+}}
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[ADD2]], v{{[0-9]+}}
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define amdgpu_kernel void @reassoc_v2i32(<2 x i32> addrspace(1)* %arg, <2 x i32> %x, <2 x i32> %y) {
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bb:
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%t1 = tail call i32 @llvm.amdgcn.workitem.id.x()
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%t2 = tail call i32 @llvm.amdgcn.workitem.id.y()
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%v1 = insertelement <2 x i32> undef, i32 %t1, i32 0
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%v2 = insertelement <2 x i32> %v1, i32 %t2, i32 1
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%add1 = add <2 x i32> %x, %v2
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%add2 = add <2 x i32> %add1, %y
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store <2 x i32> %add2, <2 x i32> addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: reassoc_i32_nuw:
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; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
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; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD1]], v{{[0-9]+}}
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[ADD1]], v{{[0-9]+}}
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define amdgpu_kernel void @reassoc_i32_nuw(i32 addrspace(1)* %arg, i32 %x, i32 %y) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add1 = add i32 %x, %tid
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%add2 = add nuw i32 %add1, %y
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store i32 %add2, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; GCN-LABEL: reassoc_i32_multiuse:
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; GFX8: v_add_u32_e32 [[ADD1:v[0-9]+]], vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_u32_e32 [[ADD1:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}
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; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, [[ADD1]]
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[ADD1]]
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define amdgpu_kernel void @reassoc_i32_multiuse(i32 addrspace(1)* %arg, i32 %x, i32 %y) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add1 = add i32 %x, %tid
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%add2 = add i32 %add1, %y
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store volatile i32 %add1, i32 addrspace(1)* %arg, align 4
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store volatile i32 %add2, i32 addrspace(1)* %arg, align 4
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ret void
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}
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; TODO: This should be reassociated as well, however it is disabled to avoid endless
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; loop since DAGCombiner::ReassociateOps() reverts the reassociation.
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; GCN-LABEL: reassoc_i32_const:
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; GFX8: v_add_u32_e32 [[ADD1:v[0-9]+]], vcc, 42, v{{[0-9]+}}
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; GFX9: v_add_u32_e32 [[ADD1:v[0-9]+]], 42, v{{[0-9]+}}
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; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, [[ADD1]]
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[ADD1]]
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define amdgpu_kernel void @reassoc_i32_const(i32 addrspace(1)* %arg, i32 %x) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add1 = add i32 %tid, 42
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%add2 = add i32 %add1, %x
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store volatile i32 %add1, i32 addrspace(1)* %arg, align 4
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store volatile i32 %add2, i32 addrspace(1)* %arg, align 4
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ret void
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}
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@var = common hidden local_unnamed_addr addrspace(1) global [4 x i32] zeroinitializer, align 4
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; GCN-LABEL: reassoc_i32_ga:
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; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, var@rel32@lo+4
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; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, var@rel32@hi+12
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; GCN: s_endpgm
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define amdgpu_kernel void @reassoc_i32_ga(i64 %x) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%t64 = zext i32 %tid to i64
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%add1 = getelementptr [4 x i32], [4 x i32] addrspace(1)* @var, i64 0, i64 %t64
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%add2 = getelementptr i32, i32 addrspace(1)* %add1, i64 %x
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store volatile i32 1, i32 addrspace(1)* %add2, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.workitem.id.y()
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