mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 12:43:36 +01:00
cc12b285b6
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
70 lines
3.6 KiB
YAML
70 lines
3.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
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# This would assert that a dead def should have no uses, but the dead
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# def and use have different subreg indices.
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---
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name: multi_def_dead_reg_subreg_check
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr24_sgpr25_sgpr26_sgpr27'
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frameOffsetReg: '$sgpr32'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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privateSegmentWaveByteOffset: { reg: '$sgpr33' }
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body: |
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; CHECK-LABEL: name: multi_def_dead_reg_subreg_check
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $sgpr6_sgpr7
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; CHECK: undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 0, [[V_MOV_B32_e32_]], implicit $exec
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; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[COPY:%[0-9]+]]:vreg_512 = COPY %0
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, implicit $exec :: (store (s32), align 8, addrspace 5)
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; CHECK: dead %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec
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; CHECK: dead %8:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
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; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
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; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
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; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
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; CHECK: %11.sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
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; CHECK: %11.sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_]]
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; CHECK: [[COPY2:%[0-9]+]]:vreg_512 = COPY %11
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; CHECK: dead %10:vgpr_32 = V_ADD_CO_U32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
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; CHECK: S_BRANCH %bb.1
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bb.0:
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liveins: $sgpr6_sgpr7
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undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%2:vgpr_32 = V_ADD_U32_e32 0, %1, implicit $exec
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%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:vreg_512 = COPY %0
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bb.1:
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BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, 0, implicit $exec :: (store (s32), align 8, addrspace 5)
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%6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec
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%8:vreg_64 = DS_READ_B64_gfx9 %1, 0, 0, implicit $exec
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%9:vreg_128 = DS_READ_B128_gfx9 %2, 0, 0, implicit $exec
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%10:vgpr_32 = V_ADD_CO_U32_e32 4, %3, implicit-def dead $vcc, implicit $exec
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undef %11.sub0:vreg_512 = COPY %4.sub0
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%12:vgpr_32 = COPY %4.sub0
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%11.sub1:vreg_512 = COPY %4.sub1
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INLINEASM &"", 1, 851978, def dead %12, 851978, def dead %4.sub1, 2147483657, %12, 2147549193, %4.sub1
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%11.sub2:vreg_512 = COPY undef %1
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%11.sub3:vreg_512 = COPY %4.sub3
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%11.sub5:vreg_512 = COPY undef %1
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%4:vreg_512 = COPY %11
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S_BRANCH %bb.1
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...
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