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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
332 lines
9.3 KiB
YAML
332 lines
9.3 KiB
YAML
# RUN: llc -run-pass=si-insert-waitcnts -march=amdgcn -mcpu=tahiti -o - %s | FileCheck %s -check-prefixes=CHECK,SI
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# RUN: llc -run-pass=si-insert-waitcnts -march=amdgcn -mcpu=gfx900 -o - %s | FileCheck %s -check-prefixes=CHECK,GFX9
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# RUN: llc -run-pass=si-insert-waitcnts -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -o - %s | FileCheck %s
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---
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# CHECK-LABEL: name: vccz_corrupt_workaround
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# CHECK: $vcc = V_CMP_EQ_F32
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
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name: vccz_corrupt_workaround
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0
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$sgpr7 = S_MOV_B32 61440
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$sgpr6 = S_MOV_B32 -1
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$vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $mode, implicit $exec
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S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
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bb.2:
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liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
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$vgpr0 = V_MOV_B32_e32 9, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.3
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bb.1:
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liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
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$vgpr0 = V_MOV_B32_e32 100, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 1, implicit $exec
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bb.3:
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liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
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$sgpr3 = S_MOV_B32 61440
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$sgpr2 = S_MOV_B32 -1
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# CHECK-LABEL: name: vccz_corrupt_undef_vcc
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# CHECK: BUFFER_STORE_DWORD_OFFSET
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# SI-NEXT: S_WAITCNT 3855
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# CHECK-NEXT: $vgpr0 = V_MOV_B32_e32
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name: vccz_corrupt_undef_vcc
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0
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$sgpr7 = S_MOV_B32 61440
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$sgpr6 = S_MOV_B32 -1
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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bb.2:
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liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
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$vgpr0 = V_MOV_B32_e32 9, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.3
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bb.1:
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liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
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$vgpr0 = V_MOV_B32_e32 100, implicit $exec
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 1, implicit $exec
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bb.3:
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liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
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$sgpr3 = S_MOV_B32 61440
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$sgpr2 = S_MOV_B32 -1
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BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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---
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# Test that after reloading vcc spilled to a vgpr, we insert any necessary
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# instructions to fix vccz.
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# CHECK-LABEL: name: reload_vcc_from_vgpr
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# CHECK: $vcc_lo = V_READLANE_B32 $vgpr0, 8, implicit-def $vcc
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# CHECK: $vcc_hi = V_READLANE_B32 $vgpr0, 9
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# SI: $vcc = S_MOV_B64 $vcc
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# GFX9: $vcc = S_MOV_B64 $vcc
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# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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name: reload_vcc_from_vgpr
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body: |
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bb.0:
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$vcc_lo = V_READLANE_B32 $vgpr0, 8, implicit-def $vcc
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$vcc_hi = V_READLANE_B32 $vgpr0, 9
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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bb.1:
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...
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---
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# Test that after reloading vcc spilled to memory, we insert any necessary
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# instructions to fix vccz.
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# CHECK-LABEL: name: reload_vcc_from_mem
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# CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec
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# CHECK: $vcc_lo = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc
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# CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, implicit $exec
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# CHECK: $vcc_hi = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc
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# SI: $vcc = S_MOV_B64 $vcc
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# GFX9: $vcc = S_MOV_B64 $vcc
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# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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name: reload_vcc_from_mem
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body: |
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bb.0:
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$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec
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$vcc_lo = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc
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$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, implicit $exec
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$vcc_hi = V_READFIRSTLANE_B32 killed $vgpr0, implicit $exec, implicit-def $vcc
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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bb.1:
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...
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---
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# Test that after inline asm that defines vcc_lo, we insert any necessary
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# instructions to fix vccz.
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# CHECK-LABEL: name: inlineasm_def_vcc_lo
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# CHECK: INLINEASM &"; def vcc_lo", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc_lo
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# SI: $vcc = S_MOV_B64 $vcc
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# GFX9: $vcc = S_MOV_B64 $vcc
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# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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name: inlineasm_def_vcc_lo
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body: |
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bb.0:
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INLINEASM &"; def vcc_lo", 1, 10, implicit-def $vcc_lo
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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bb.1:
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...
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---
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# Test that after inline asm that defines vcc, no unnecessary instructions are
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# inserted to fix vccz.
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# CHECK-LABEL: name: inlineasm_def_vcc
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# CHECK: INLINEASM &"; def vcc", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc
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# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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name: inlineasm_def_vcc
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body: |
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bb.0:
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INLINEASM &"; def vcc", 1, 10, implicit-def $vcc
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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bb.1:
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...
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---
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# Test vcc definition in a previous basic block.
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# CHECK-LABEL: name: vcc_def_pred
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# CHECK: bb.1:
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# SI: $vcc = S_MOV_B64 $vcc
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# GFX9: $vcc = S_MOV_B64 $vcc
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# CHECK: S_CBRANCH_VCCZ %bb.2, implicit $vcc
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name: vcc_def_pred
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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bb.1:
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S_CBRANCH_VCCZ %bb.2, implicit $vcc
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bb.2:
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...
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# Test various ways that the live range of vccz can overlap with the live range
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# of an outstanding smem load.
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---
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# CHECK-LABEL: name: load_wait_def_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_wait_def_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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S_WAITCNT 127
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$vcc = S_MOV_B64 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: load_wait_nop_def_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: S_NOP 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_wait_nop_def_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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S_WAITCNT 127
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S_NOP 0
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$vcc = S_MOV_B64 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: load_def_wait_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_def_wait_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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$vcc = S_MOV_B64 0
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S_WAITCNT 127
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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# CHECK-LABEL: name: load_def_wait_nop_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: S_NOP 0
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_def_wait_nop_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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$vcc = S_MOV_B64 0
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S_WAITCNT 127
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S_NOP 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: load_def_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: load_def_use
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body: |
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bb.0:
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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$vcc = S_MOV_B64 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: def_load_wait_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: def_load_wait_use
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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S_WAITCNT 127
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: def_load_wait_nop_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: S_NOP 0
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: def_load_wait_nop_use
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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S_WAITCNT 127
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S_NOP 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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---
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# CHECK-LABEL: name: def_load_use
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# SI: S_WAITCNT 0
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# SI-NEXT: $vcc = S_MOV_B64 0
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# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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# SI-NEXT: S_WAITCNT 127
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# SI-NEXT: $vcc = S_MOV_B64 $vcc
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# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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name: def_load_use
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body: |
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bb.0:
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$vcc = S_MOV_B64 0
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$sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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