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196e7f3138
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
27 lines
871 B
YAML
27 lines
871 B
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-insert-waitcnts -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# Check that the waitcnt propogates info in the case of a single basic block loop
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# GCN-LABEL: waitcnt-loop-single-basic-block
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# GCN: bb.0
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# GCN: S_WAITCNT 3952
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# GCN-NEXT: GLOBAL_STORE_DWORD
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# GCN: S_WAITCNT 3953
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# GCN-NEXT: GLOBAL_STORE_DWORD
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...
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name: waitcnt-loop-single-basic-block
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body: |
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bb.0:
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S_BRANCH %bb.1
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bb.1:
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GLOBAL_STORE_DWORD $vgpr7_vgpr8, $vgpr11, 0, 0, implicit $exec
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$vgpr21 = GLOBAL_LOAD_DWORD $vgpr4_vgpr5, 0, 0, implicit $exec
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$vgpr10 = GLOBAL_LOAD_DWORD $vgpr10_vgpr11, 0, 0, implicit $exec
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GLOBAL_STORE_DWORD $vgpr14_vgpr15, $vgpr21, 0, 0, implicit $exec
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$vgpr11 = GLOBAL_LOAD_DWORD $vgpr11_vgpr12, 0, 0, implicit $exec
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...
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