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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
90 lines
3.1 KiB
LLVM
90 lines
3.1 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv5e-none-linux-gnueabi | FileCheck %s
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; PR8986: PostRA antidependence breaker must respect "earlyclobber".
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; armv5e generates mulv5 that cannot used the same reg for src/dest.
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; ModuleID = '<stdin>'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32"
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target triple = "armv5e-none-linux-gnueabi"
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define hidden fastcc void @storeAtts() nounwind {
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entry:
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%.SV116 = alloca i8**
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br i1 undef, label %meshBB520, label %meshBB464
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bb15: ; preds = %meshBB424
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br i1 undef, label %bb216, label %meshBB396
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bb22: ; preds = %meshBB396
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br label %cBB564
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cBB564: ; preds = %cBB564, %bb22
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br label %cBB564
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poolStoreString.exit.thread: ; preds = %meshBB424
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ret void
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bb78: ; preds = %meshBB412
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unreachable
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bb129: ; preds = %meshBB540
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br i1 undef, label %bb131.loopexit, label %meshBB540
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bb131.loopexit: ; preds = %bb129
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br label %bb131
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bb131: ; preds = %bb135, %bb131.loopexit
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br i1 undef, label %bb134, label %meshBB396
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bb134: ; preds = %bb131
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unreachable
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bb135: ; preds = %meshBB396
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%uriHash.1.phi.load = load i32, i32* undef
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%.load120 = load i8**, i8*** %.SV116
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%.phi24 = load i8, i8* null
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%.phi26 = load i8*, i8** null
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store i8 %.phi24, i8* %.phi26, align 1
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%0 = getelementptr inbounds i8, i8* %.phi26, i32 1
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store i8* %0, i8** %.load120, align 4
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; CHECK: mul [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{(lr|r[0-9]+)$}}
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%1 = mul i32 %uriHash.1.phi.load, 1000003
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%2 = xor i32 0, %1
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store i32 %2, i32* null
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%3 = load i8, i8* null, align 1
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%4 = icmp eq i8 %3, 0
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store i8* %0, i8** undef
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br i1 %4, label %meshBB472, label %bb131
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bb212: ; preds = %meshBB540
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unreachable
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bb216: ; preds = %bb15
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ret void
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meshBB396: ; preds = %bb131, %bb15
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br i1 undef, label %bb135, label %bb22
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meshBB412: ; preds = %meshBB464
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br i1 undef, label %meshBB504, label %bb78
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meshBB424: ; preds = %meshBB464
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br i1 undef, label %poolStoreString.exit.thread, label %bb15
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meshBB464: ; preds = %entry
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br i1 undef, label %meshBB424, label %meshBB412
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meshBB472: ; preds = %meshBB504, %bb135
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unreachable
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meshBB504: ; preds = %meshBB412
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br label %meshBB472
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meshBB520: ; preds = %entry
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br label %meshBB540
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meshBB540: ; preds = %meshBB520, %bb129
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br i1 undef, label %bb212, label %bb129
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}
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