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a3957bd3b3
This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 llvm-svn: 360768
107 lines
3.5 KiB
LLVM
107 lines
3.5 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-linux-gnueabihf -o - | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK-M4F
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
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define arm_aapcs_vfpcc void @test_1float({ float } %a) {
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call arm_aapcs_vfpcc void @test_1float({ float } { float 1.0 })
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ret void
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; CHECK-LABEL: test_1float:
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; CHECK-DAG: vmov.f32 s0, #1.{{0+}}e+00
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; CHECK: bl test_1float
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; CHECK-M4F-LABEL: test_1float:
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; CHECK-M4F-DAG: vmov.f32 s0, #1.{{0+}}e+00
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; CHECK-M4F: bl test_1float
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}
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define arm_aapcs_vfpcc void @test_2float({ float, float } %a) {
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call arm_aapcs_vfpcc void @test_2float({ float, float } { float 1.0, float 2.0 })
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ret void
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; CHECK-LABEL: test_2float:
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; CHECK-DAG: vmov.f32 s0, #1.{{0+}}e+00
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; CHECK-DAG: vmov.f32 s1, #2.{{0+}}e+00
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; CHECK: bl test_2float
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; CHECK-M4F-LABEL: test_2float:
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; CHECK-M4F-DAG: vmov.f32 s0, #1.{{0+}}e+00
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; CHECK-M4F-DAG: vmov.f32 s1, #2.{{0+}}e+00
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; CHECK-M4F: bl test_2float
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}
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define arm_aapcs_vfpcc void @test_3float({ float, float, float } %a) {
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call arm_aapcs_vfpcc void @test_3float({ float, float, float } { float 1.0, float 2.0, float 3.0 })
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ret void
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; CHECK-LABEL: test_3float:
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; CHECK-DAG: vmov.f32 s0, #1.{{0+}}e+00
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; CHECK-DAG: vmov.f32 s1, #2.{{0+}}e+00
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; CHECK-DAG: vmov.f32 s2, #3.{{0+}}e+00
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; CHECK: bl test_3float
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; CHECK-M4F-LABEL: test_3float:
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; CHECK-M4F-DAG: vmov.f32 s0, #1.{{0+}}e+00
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; CHECK-M4F-DAG: vmov.f32 s1, #2.{{0+}}e+00
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; CHECK-M4F-DAG: vmov.f32 s2, #3.{{0+}}e+00
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; CHECK-M4F: bl test_3float
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}
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define arm_aapcs_vfpcc void @test_1double({ double } %a) {
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; CHECK-LABEL: test_1double:
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; CHECK-DAG: vmov.f64 d0, #1.{{0+}}e+00
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; CHECK: bl test_1double
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; CHECK-M4F-LABEL: test_1double:
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; CHECK-M4F: vldr d0, [[CP_LABEL:.*]]
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; CHECK-M4F: bl test_1double
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; CHECK-M4F: [[CP_LABEL]]
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; CHECK-M4F-NEXT: .long 0
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; CHECK-M4F-NEXT: .long 1072693248
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call arm_aapcs_vfpcc void @test_1double({ double } { double 1.0 })
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ret void
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}
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; Final double argument might be put in s15 & [sp] if we're careless. It should
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; go all on the stack.
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define arm_aapcs_vfpcc void @test_1double_nosplit([4 x float], [4 x double], [3 x float], double %a) {
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; CHECK-LABEL: test_1double_nosplit:
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; CHECK-DAG: mov [[ONELO:r[0-9]+]], #0
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; CHECK-DAG: movw [[ONEHI:r[0-9]+]], #0
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; CHECK-DAG: movt [[ONEHI]], #16368
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; CHECK: strd [[ONELO]], [[ONEHI]], [sp]
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; CHECK: bl test_1double_nosplit
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; CHECK-M4F-LABEL: test_1double_nosplit:
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; CHECK-M4F: movs [[ONEHI:r[0-9]+]], #0
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; CHECK-M4F: movt [[ONEHI]], #16368
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; CHECK-M4F: movs [[ONELO:r[0-9]+]], #0
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; CHECK-M4F: strd [[ONELO]], [[ONEHI]], [sp]
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; CHECK-M4F: bl test_1double_nosplit
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call arm_aapcs_vfpcc void @test_1double_nosplit([4 x float] undef, [4 x double] undef, [3 x float] undef, double 1.0)
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ret void
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}
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; Final double argument might go at [sp, #4] if we're careless. Should go at
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; [sp, #8] to preserve alignment.
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define arm_aapcs_vfpcc void @test_1double_misaligned([4 x double], [4 x double], float, double) {
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call arm_aapcs_vfpcc void @test_1double_misaligned([4 x double] undef, [4 x double] undef, float undef, double 1.0)
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; CHECK-LABEL: test_1double_misaligned:
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; CHECK-DAG: movw [[ONEHI:r[0-9]+]], #0
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; CHECK-DAG: mov [[ONELO:r[0-9]+]], #0
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; CHECK-DAG: movt [[ONEHI]], #16368
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; CHECK-DAG: strd [[ONELO]], [[ONEHI]], [sp, #8]
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; CHECK-M4F-LABEL: test_1double_misaligned:
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; CHECK-M4F: movs [[ONEHI:r[0-9]+]], #0
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; CHECK-M4F: movt [[ONEHI]], #16368
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; CHECK-M4F: movs [[ONELO:r[0-9]+]], #0
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; CHECK-M4F: strd [[ONELO]], [[ONEHI]], [sp, #8]
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; CHECK-M4F: bl test_1double_misaligned
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ret void
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}
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