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If an FP_EXTEND or FP_ROUND isel dag node converts directly between f16 and f32 when the target CPU has no instruction to do it in one go, it has to be done in two steps instead, going via f32. Previously, this was done implicitly, because all such CPUs had the storage-only implementation of f16 (i.e. the only thing you can do with one at all is to convert it to/from f32). So isel would legalize the f16 into an f32 as soon as it saw it, by inserting an fp16_to_fp node (or vice versa), and then the fp_extend would already be f32->f64 rather than f16->f64. But that technique can't support a target CPU which has full f16 support but _not_ f64, such as some variants of Arm v8.1-M. So now we provide custom lowering for FP_EXTEND and FP_ROUND, which checks support for f16 and f64 and decides on the best thing to do given the combination of flags it gets back. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60692 llvm-svn: 364294
86 lines
2.8 KiB
LLVM
86 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-OLD
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; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-F16
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; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
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; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
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; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
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; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8
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; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8,-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP
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; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8
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; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP
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define void @test_load_store(half* %in, half* %out) {
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; CHECK-LABEL: test_load_store:
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; CHECK: ldrh [[TMP:r[0-9]+]], [r0]
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; CHECK: strh [[TMP]], [r1]
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%val = load half, half* %in
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store half %val, half* %out
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ret void
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}
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define i16 @test_bitcast_from_half(half* %addr) {
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; CHECK-LABEL: test_bitcast_from_half:
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; CHECK: ldrh r0, [r0]
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%val = load half, half* %addr
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%val_int = bitcast half %val to i16
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ret i16 %val_int
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}
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define void @test_bitcast_to_half(half* %addr, i16 %in) {
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; CHECK-LABEL: test_bitcast_to_half:
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; CHECK: strh r1, [r0]
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%val_fp = bitcast i16 %in to half
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store half %val_fp, half* %addr
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ret void
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}
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define float @test_extend32(half* %addr) {
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; CHECK-LABEL: test_extend32:
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; CHECK-OLD: b.w ___extendhfsf2
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; CHECK-F16: vcvtb.f32.f16
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; CHECK-V8: vcvtb.f32.f16
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; CHECK-V8-SP: vcvtb.f32.f16
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to float
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ret float %val32
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}
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define double @test_extend64(half* %addr) {
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; CHECK-LABEL: test_extend64:
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; CHECK-OLD: bl ___extendhfsf2
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; CHECK-OLD: vcvt.f64.f32
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; CHECK-F16: vcvtb.f32.f16
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; CHECK-F16: vcvt.f64.f32
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; CHECK-V8: vcvtb.f64.f16
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; CHECK-V8-SP: vcvtb.f32.f16
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; CHECK-V8-SP: bl __aeabi_f2d
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to double
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ret double %val32
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}
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define void @test_trunc32(float %in, half* %addr) {
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; CHECK-LABEL: test_trunc32:
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; CHECK-OLD: bl ___truncsfhf2
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; CHECK-F16: vcvtb.f16.f32
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; CHECK-V8: vcvtb.f16.f32
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; CHECK-V8-SP: vcvtb.f16.f32
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%val16 = fptrunc float %in to half
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store half %val16, half* %addr
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ret void
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}
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define void @test_trunc64(double %in, half* %addr) {
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; CHECK-LABEL: test_trunc64:
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; CHECK-OLD: bl ___truncdfhf2
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; CHECK-F16: bl ___truncdfhf2
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; CHECK-V8: vcvtb.f16.f64
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; CHECK-V8-SP: bl __aeabi_d2h
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%val16 = fptrunc double %in to half
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store half %val16, half* %addr
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ret void
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}
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