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https://github.com/RPCS3/llvm-mirror.git
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3100a6e21e
IT blocks with more than one instruction were performance deprecated in Armv8 but that doesn't mean we should follow that advise when optimising for size. Differential Revision: https://reviews.llvm.org/D85638
562 lines
15 KiB
YAML
562 lines
15 KiB
YAML
# RUN: llc -mtriple=thumbv8a-unknown-linux-gnueabi %s -o - -run-pass=if-converter -debug-only=if-converter | FileCheck %s
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# RUN: llc -mtriple=thumbv7-unknown-linux-gnueabi %s -o - -run-pass=if-converter -debug-only=if-converter 2>%t| FileCheck %s
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# RUN: FileCheck %s < %t --check-prefix=DEBUG
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# REQUIRES: asserts
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# When optimising for size, we use a different set of heuristics for
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# if-conversion, which take into account the size of the instructions, not the
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# time taken to execute them. This is more complicated for Thumb, where it if
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# also affected by selection of narrow branch instructions, insertion if IT
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# instructions, and selection of the CB(N)Z instructions.
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--- |
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define void @fn1() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn2() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn3() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn4() minsize "target-features"="-thumb-mode" {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn5() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn6() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if2.then:
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unreachable
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if2.else:
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unreachable
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}
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define void @fn7() minsize "target-features"="-thumb-mode" {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn8() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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if.end:
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unreachable
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}
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define void @fn9() minsize {
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entry:
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unreachable
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if.then:
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unreachable
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if.else:
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unreachable
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lab1:
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unreachable
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}
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...
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---
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name: fn1
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alignment: 1
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tracksRegLiveness: true
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# If-conversion is profitable here because it will remove two branches of 2
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# bytes each (assuming they can become narrow branches later), and will only
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# add 2 bytes with the IT instruction.
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# CHECK-LABEL: name: fn1
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# CHECK: t2CMPri
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRSHi12
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# CHECK-NEXT: t2MOVi
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn1'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=4, CommonBytes=0, NumPredicatedInstructions=4, ExtraPredicateBytes=2)
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r3
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t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 11, killed $cpsr
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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liveins: $r0, $r3
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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t2B %bb.3, 14, $noreg
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bb.2.if.else:
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successors: %bb.3(0x80000000)
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liveins: $r1, $r3
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renamable $r0 = t2LDRi12 killed renamable $r1, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
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bb.3.if.end:
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liveins: $r0, $r3
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renamable $r1 = t2MOVi 0, 14, $noreg, $noreg
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t2STRi12 killed renamable $r1, killed renamable $r3, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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---
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name: fn2
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alignment: 1
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tracksRegLiveness: true
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# If-conversion is not profitable here, because the 5 conditional instructions
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# would require 2 IT instructions.
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# CHECK-LABEL: name: fn2
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# CHECK: t2CMPri
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# CHECK-NEXT: t2Bcc
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn2'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=4, CommonBytes=0, NumPredicatedInstructions=5, ExtraPredicateBytes=4)
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r3
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t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 11, killed $cpsr
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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liveins: $r0, $r3
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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t2B %bb.3, 14, $noreg
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bb.2.if.else:
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successors: %bb.3(0x80000000)
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liveins: $r1, $r3
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renamable $r0 = t2LDRi12 killed renamable $r1, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
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bb.3.if.end:
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liveins: $r0, $r3
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renamable $r1 = t2MOVi 0, 14, $noreg, $noreg
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t2STRi12 killed renamable $r1, killed renamable $r3, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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---
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name: fn3
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alignment: 1
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tracksRegLiveness: true
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# Here, the true and false blocks both end in a tBX_RET instruction. One of
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# these will be removed, saving 2 bytes, and the remaining one isn't
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# conditional, so doesn't push us over the limit of 4 instructions in an IT
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# block.
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# CHECK-LABEL: name: fn3
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# CHECK: t2CMPri
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRSHi12
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# CHECK-NEXT: tBX_RET
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn3'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=2, CommonBytes=2, NumPredicatedInstructions=4, ExtraPredicateBytes=2)
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r3
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t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 11, killed $cpsr
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bb.1.if.then:
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liveins: $r0, $r3
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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bb.2.if.else:
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liveins: $r1, $r3
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renamable $r0 = t2LDRi12 killed renamable $r1, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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---
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name: fn4
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alignment: 1
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tracksRegLiveness: true
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# This is the same as fn2, but compiled for ARM, which doesn't need IT
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# instructions, so if-conversion is profitable.
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# CHECK-LABEL: name: fn4
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# CHECK: CMPri
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# CHECK-NEXT: LDRi12
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# CHECK-NEXT: LDRi12
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# CHECK-NEXT: LDRSH
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# CHECK-NEXT: LDRi12
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# CHECK-NEXT: LDRi12
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# CHECK-NEXT: MOVi
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn4'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=8, CommonBytes=0, NumPredicatedInstructions=5, ExtraPredicateBytes=0)
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r3
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CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
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Bcc %bb.2, 11, killed $cpsr
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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liveins: $r0, $r3
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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B %bb.3
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bb.2.if.else:
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successors: %bb.3(0x80000000)
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liveins: $r1, $r3
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renamable $r0 = LDRi12 killed renamable $r1, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRSH killed renamable $r0, $noreg, 0, 14, $noreg
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bb.3.if.end:
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liveins: $r0, $r3
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renamable $r1 = MOVi 0, 14, $noreg, $noreg
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STRi12 killed renamable $r1, killed renamable $r3, 0, 14, $noreg
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BX_RET 14, $noreg, implicit $r0
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---
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name: fn5
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alignment: 1
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tracksRegLiveness: true
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# Here, the compare and conditional branch can be turned into a CBZ, so we
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# don't want to if-convert.
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# CHECK-LABEL: name: fn5
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# CHECK: t2CMPri
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# CHECK: t2Bcc
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn5'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=0, CommonBytes=2, NumPredicatedInstructions=4, ExtraPredicateBytes=2)
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body: |
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bb.0.entry:
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successors: %bb.1(0x30000000), %bb.2(0x50000000)
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liveins: $r0, $r1, $r2
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t2CMPri killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 1, killed $cpsr
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bb.1.if.then:
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liveins: $r0
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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bb.2.if.else:
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liveins: $r1
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renamable $r0 = t2LDRi12 killed renamable $r1, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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---
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name: fn6
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alignment: 1
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tracksRegLiveness: true
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# This is a forked-diamond pattern, we recognise that the conditional branches
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# at the ends of the true and false blocks are the same, and can be shared.
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# CHECK-LABEL: name: fn6
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# CHECK: t2CMPri
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# CHECK-NEXT: t2LDRSHi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2CMPri
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# CHECK-NEXT: t2Bcc
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn6'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=2, CommonBytes=12, NumPredicatedInstructions=4, ExtraPredicateBytes=2)
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body: |
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bb.0.entry:
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successors: %bb.1(0x30000000), %bb.2(0x50000000)
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liveins: $r0, $r1, $r2, $r3
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t2CMPri killed renamable $r2, 4, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 1, killed $cpsr
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bb.1.if.then:
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successors: %bb.3(0x30000000), %bb.4(0x50000000)
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liveins: $r0, $r1, $r3
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
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t2CMPri renamable $r0, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.3.if2.then, 1, killed $cpsr
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t2B %bb.4.if2.else, 14, $noreg
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bb.2.if.else:
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successors: %bb.3(0x30000000), %bb.4(0x50000000)
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liveins: $r0, $r1, $r3
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renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
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t2CMPri renamable $r0, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.3.if2.then, 1, killed $cpsr
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t2B %bb.4.if2.else, 14, $noreg
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bb.3.if2.then:
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liveins: $r0, $r1, $r3
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t2STRi12 killed renamable $r1, killed renamable $r3, 0, 14, $noreg
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tBX_RET 14, $noreg, implicit $r0
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bb.4.if2.else:
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liveins: $r0
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tBX_RET 14, $noreg, implicit $r0
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---
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name: fn7
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alignment: 1
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tracksRegLiveness: true
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# When compiling for ARM, it would be good for code size to generate very long
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# runs of conditional instructions, but we put an (arbitrary) limit on this to
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# avoid generating code which is very bad for performance, and only saves a few
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# bytes of code size.
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# CHECK-LABEL: name: fn7
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# CHECK: CMPri
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# CHECK-NEXT: Bcc
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r3
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CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
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Bcc %bb.2, 11, killed $cpsr
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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liveins: $r0, $r3
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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B %bb.3
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bb.2.if.else:
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successors: %bb.3(0x80000000)
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liveins: $r1, $r3
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renamable $r0 = LDRi12 killed renamable $r1, 0, 14, $noreg
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renamable $r0 = LDRi12 killed renamable $r0, 0, 14, $noreg
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renamable $r0 = LDRSH killed renamable $r0, $noreg, 0, 14, $noreg
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bb.3.if.end:
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liveins: $r0, $r3
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renamable $r1 = MOVi 0, 14, $noreg, $noreg
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STRi12 killed renamable $r1, killed renamable $r3, 0, 14, $noreg
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BX_RET 14, $noreg, implicit $r0
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---
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name: fn8
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alignment: 1
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tracksRegLiveness: true
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# The first t2LDRi12 instruction in each branch is the same, so one copy of it
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# will be removed, and it doesn't need to be predicated, keeping us under the 4
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# instruction IT block limit.
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# CHECK-LABEL: name: fn8
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# CHECK: t2CMPri
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRi12
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# CHECK-NEXT: t2LDRSHi12
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# CHECK-NEXT: t2MOVi
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# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn8'
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# DEBUG: MeetIfcvtSizeLimit(BranchBytes=4, CommonBytes=4, NumPredicatedInstructions=4, ExtraPredicateBytes=2)
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1, $r2, $r3
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|
|
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t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 11, killed $cpsr
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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liveins: $r0, $r3
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|
|
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
|
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renamable $r0 = t2LDRi12 killed renamable $r0, 4, 14, $noreg
|
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t2B %bb.3, 14, $noreg
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|
|
|
bb.2.if.else:
|
|
successors: %bb.3(0x80000000)
|
|
liveins: $r0, $r3
|
|
|
|
renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
|
|
renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
|
|
renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14, $noreg
|
|
renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
|
|
|
|
bb.3.if.end:
|
|
liveins: $r0, $r3
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|
|
|
renamable $r1 = t2MOVi 0, 14, $noreg, $noreg
|
|
t2STRi12 killed renamable $r1, killed renamable $r3, 0, 14, $noreg
|
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tBX_RET 14, $noreg, implicit $r0
|
|
|
|
---
|
|
name: fn9
|
|
alignment: 2
|
|
tracksRegLiveness: true
|
|
|
|
# The INLINEASM_BR instructions aren't analyzable, but they are identical so we
|
|
# can still do diamond if-conversion. From a code-size POV, they are common
|
|
# instructions, so one will be removed, and they don't need an IT block slot.
|
|
|
|
# CHECK-LABEL: name: fn9
|
|
# CHECK: tCMPi8
|
|
# CHECK-NEXT: tLDRi
|
|
# CHECK-NEXT: tLDRi
|
|
# CHECK-NEXT: tLDRi
|
|
# CHECK-NEXT: t2LDRSHi12
|
|
# CHECK-NEXT: INLINEASM_BR
|
|
|
|
# DEBUG-LABEL: Ifcvt: function ({{[0-9]+}}) 'fn9'
|
|
# DEBUG: MeetIfcvtSizeLimit(BranchBytes=2, CommonBytes=8, NumPredicatedInstructions=4, ExtraPredicateBytes=2)
|
|
|
|
body: |
|
|
bb.0.entry:
|
|
successors: %bb.1(0x30000000), %bb.3(0x50000000)
|
|
liveins: $r0, $r1, $r2
|
|
|
|
tCMPi8 renamable $r2, 42, 14, $noreg, implicit-def $cpsr
|
|
t2Bcc %bb.3, 1, killed $cpsr
|
|
|
|
bb.1.if.then:
|
|
successors: %bb.5(0x7fffffff)
|
|
liveins: $r0, $r2
|
|
|
|
renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg
|
|
INLINEASM_BR &"b ${0:l}", 1, 13, blockaddress(@fn9, %ir-block.lab1)
|
|
tBX_RET 14, $noreg, implicit $r2
|
|
|
|
bb.3.if.else:
|
|
successors: %bb.5(0x7fffffff)
|
|
liveins: $r1, $r2
|
|
|
|
renamable $r0 = tLDRi killed renamable $r1, 0, 14, $noreg
|
|
renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg
|
|
renamable $r0 = t2LDRSHi12 killed renamable $r0, 0, 14, $noreg
|
|
INLINEASM_BR &"b ${0:l}", 1, 13, blockaddress(@fn9, %ir-block.lab1)
|
|
tBX_RET 14, $noreg, implicit $r2
|
|
|
|
bb.5.lab1 (address-taken):
|
|
liveins: $r0
|
|
|
|
renamable $r0, dead $cpsr = nsw tADDi8 killed renamable $r0, 5, 14, $noreg
|
|
tBX_RET 14, $noreg, implicit $r0
|
|
...
|