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1031830a08
r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 llvm-svn: 372186
21 lines
927 B
LLVM
21 lines
927 B
LLVM
; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfp2sp %s -o - | FileCheck %s -check-prefixes=COMMON,NOVFP
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; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefixes=COMMON,VFP
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; The intent here is to test "X", which says that any operand whatsoever is allowed.
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; Using this mechanism, we want to test toggling allocating GPR or SPR registers
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; depending on whether the float registers are available. Thus, the mnemonic is
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; totally irrelevant here, which is why we use FOO and also comment it out using "@"
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; to avoid assembler errors.
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; Note that this kind of IR can be generated by a function such as:
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; void f1(float f) {asm volatile ("@FOO $0, $0" : : "X" (f));}
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define arm_aapcs_vfpcc void @func(float %f) {
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; COMMON-LABEL: func
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; NOVFP: FOO r0, r0
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; VFP: FOO s0, s0
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entry:
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call void asm sideeffect "@FOO $0, $0", "X" (float %f) nounwind
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ret void
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}
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