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llvm-mirror/test/CodeGen/ARM/xray-tail-call-sled.ll
Fangrui Song 21cd444174 [XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address)
Follow-up of D78082 (x86-64).

This change avoids dynamic relocations in `xray_instr_map` for ARM/AArch64/powerpc64le.

MIPS64 cannot use 64-bit PC-relative addresses because R_MIPS_PC64 is not defined.
Because MIPS32 shares the same code, for simplicity, we don't use PC-relative addresses for MIPS32 as well.

Tested on AArch64 Linux and ppc64le Linux.

Reviewed By: ianlevesque

Differential Revision: https://reviews.llvm.org/D78590
2020-04-24 08:35:43 -07:00

55 lines
1.3 KiB
LLVM

; RUN: llc -filetype=asm -o - -mtriple=armv7-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -filetype=asm -o - -mtriple=armv7-apple-ios6.0.0 < %s | FileCheck %s
define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK: .p2align 2
; CHECK-LABEL: Lxray_sled_0:
; CHECK-NEXT: b #20
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-LABEL: Ltmp0:
ret i32 0
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: .p2align 2
; CHECK-LABEL: Lxray_sled_1:
; CHECK-NEXT: b #20
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-LABEL: Ltmp1:
; CHECK-NEXT: bx lr
}
define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK: .p2align 2
; CHECK-LABEL: Lxray_sled_2:
; CHECK-NEXT: b #20
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-LABEL: Ltmp4:
; CHECK: .p2align 2
; CHECK-LABEL: Lxray_sled_3:
; CHECK-NEXT: b #20
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-NEXT: nop
; CHECK-LABEL: Ltmp5:
%retval = tail call i32 @callee()
; CHECK: b {{.*}}callee
ret i32 %retval
}