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72 lines
2.2 KiB
LLVM
72 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
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declare void @llvm.ppc.dcbtstt(i8*)
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declare void @llvm.ppc.dcbtt(i8*)
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@vpa = external local_unnamed_addr global i8*, align 8
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define dso_local void @test_dcbtstt() {
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; CHECK-LABEL: test_dcbtstt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: dcbtstt 0, 3
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; CHECK-NEXT: blr
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;
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; CHECK-AIX-LABEL: test_dcbtstt:
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; CHECK-AIX: # %bb.0: # %entry
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; CHECK-AIX-NEXT: lwz 3, L..C0(2) # @vpa
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; CHECK-AIX-NEXT: lwz 3, 0(3)
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; CHECK-AIX-NEXT: dcbtstt 0, 3
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; CHECK-AIX-NEXT: blr
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;
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; CHECK-AIX64-LABEL: test_dcbtstt:
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; CHECK-AIX64: # %bb.0: # %entry
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; CHECK-AIX64-NEXT: ld 3, L..C0(2) # @vpa
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; CHECK-AIX64-NEXT: ld 3, 0(3)
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; CHECK-AIX64-NEXT: dcbtstt 0, 3
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; CHECK-AIX64-NEXT: blr
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entry:
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%0 = load i8*, i8** @vpa, align 8
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tail call void @llvm.ppc.dcbtstt(i8* %0)
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ret void
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}
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define dso_local void @test_dcbtt() {
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; CHECK-LABEL: test_dcbtt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: dcbtt 0, 3
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; CHECK-NEXT: blr
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;
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; CHECK-AIX-LABEL: test_dcbtt:
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; CHECK-AIX: # %bb.0: # %entry
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; CHECK-AIX-NEXT: lwz 3, L..C0(2) # @vpa
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; CHECK-AIX-NEXT: lwz 3, 0(3)
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; CHECK-AIX-NEXT: dcbtt 0, 3
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; CHECK-AIX-NEXT: blr
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;
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; CHECK-AIX64-LABEL: test_dcbtt:
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; CHECK-AIX64: # %bb.0: # %entry
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; CHECK-AIX64-NEXT: ld 3, L..C0(2) # @vpa
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; CHECK-AIX64-NEXT: ld 3, 0(3)
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; CHECK-AIX64-NEXT: dcbtt 0, 3
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; CHECK-AIX64-NEXT: blr
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entry:
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%0 = load i8*, i8** @vpa, align 8
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tail call void @llvm.ppc.dcbtt(i8* %0)
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ret void
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}
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