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9f4ca39c11
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
65 lines
2.8 KiB
LLVM
65 lines
2.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \
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; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \
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; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \
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; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \
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; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=medium \
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; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=large \
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; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-P9 %s
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; Test correct code generation for medium and large code model
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; for loading a value from the constant pool (TOC-relative).
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @test_double_const() nounwind {
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entry:
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ret double 0x3F4FD4920B498CF0
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}
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; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
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; MEDIUM: .quad 0x3f4fd4920b498cf0
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; MEDIUM-LABEL: test_double_const:
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; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
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; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
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; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
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; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
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; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0
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; MEDIUM-VSX-LABEL: test_double_const:
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; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
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; MEDIUM-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}})
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; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
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; LARGE: .quad 0x3f4fd4920b498cf0
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; LARGE-LABEL: test_double_const:
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; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
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; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
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; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
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; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
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; LARGE-VSX: .quad 0x3f4fd4920b498cf0
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; LARGE-VSX-LABEL: test_double_const:
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; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
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; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
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; LARGE-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}})
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; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
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; MEDIUM-P9: .quad 0x3f4fd4920b498cf0
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; MEDIUM-P9-LABEL: test_double_const:
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; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
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; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
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; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]])
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; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]:
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; LARGE-P9: .quad 0x3f4fd4920b498cf0
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; LARGE-P9-LABEL: test_double_const:
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; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
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; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
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; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]])
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