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https://github.com/RPCS3/llvm-mirror.git
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19f5254989
Summary: PPC only supports the instruction selection for v16i8, v8i16, v4i32, v2i64, v4f32 and v2f64 for ISD::SETCC, don't support the v1i128, so v1i128 for ISD::SETCC will crash. This patch is to set v1i128 to expand to avoid crash. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D84238
50 lines
1.9 KiB
LLVM
50 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR9 %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR8 %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR7 %s
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define <1 x i64> @setcc_v1i128(<1 x i128> %a) {
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; CHECK-PWR9-LABEL: setcc_v1i128:
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; CHECK-PWR9: # %bb.0: # %entry
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; CHECK-PWR9-NEXT: mfvsrld r3, vs34
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; CHECK-PWR9-NEXT: cmpldi r3, 35708
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; CHECK-PWR9-NEXT: mfvsrd r3, vs34
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; CHECK-PWR9-NEXT: cmpdi cr1, r3, 0
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; CHECK-PWR9-NEXT: li r3, 1
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; CHECK-PWR9-NEXT: crnand 4*cr5+lt, 4*cr1+eq, lt
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; CHECK-PWR9-NEXT: isel r3, 0, r3, 4*cr5+lt
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; CHECK-PWR9-NEXT: blr
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;
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; CHECK-PWR8-LABEL: setcc_v1i128:
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; CHECK-PWR8: # %bb.0: # %entry
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; CHECK-PWR8-NEXT: xxswapd vs0, vs34
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; CHECK-PWR8-NEXT: mfvsrd r3, vs34
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; CHECK-PWR8-NEXT: cmpdi r3, 0
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; CHECK-PWR8-NEXT: li r3, 1
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; CHECK-PWR8-NEXT: mffprd r4, f0
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; CHECK-PWR8-NEXT: cmpldi cr1, r4, 35708
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; CHECK-PWR8-NEXT: crnand 4*cr5+lt, eq, 4*cr1+lt
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; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt
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; CHECK-PWR8-NEXT: blr
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;
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; CHECK-PWR7-LABEL: setcc_v1i128:
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; CHECK-PWR7: # %bb.0: # %entry
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; CHECK-PWR7-NEXT: li r5, 0
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; CHECK-PWR7-NEXT: cntlzd r3, r3
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; CHECK-PWR7-NEXT: ori r5, r5, 35708
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; CHECK-PWR7-NEXT: rldicl r3, r3, 58, 63
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; CHECK-PWR7-NEXT: subc r5, r4, r5
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; CHECK-PWR7-NEXT: subfe r4, r4, r4
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; CHECK-PWR7-NEXT: neg r4, r4
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; CHECK-PWR7-NEXT: and r3, r3, r4
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; CHECK-PWR7-NEXT: blr
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entry:
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%0 = icmp ult <1 x i128> %a, <i128 35708>
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%1 = zext <1 x i1> %0 to <1 x i64>
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ret <1 x i64> %1
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}
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