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279 lines
8.4 KiB
LLVM
279 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
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@CVal = external local_unnamed_addr global i8, align 1
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@SVal = external local_unnamed_addr global i16, align 2
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@IVal = external local_unnamed_addr global i32, align 4
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@LVal = external local_unnamed_addr global i64, align 8
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@USVal = external local_unnamed_addr global i16, align 2
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@arr = external local_unnamed_addr global i64*, align 8
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@arri = external local_unnamed_addr global i32*, align 8
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; Test the same constant can be used by different stores.
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%struct.S = type { i64, i8, i16, i32 }
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define void @foo(%struct.S* %p) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: stb 4, 8(3)
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; CHECK-NEXT: std 4, 0(3)
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; CHECK-NEXT: sth 4, 10(3)
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; CHECK-NEXT: stw 4, 12(3)
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; CHECK-NEXT: blr
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%l4 = bitcast %struct.S* %p to i64*
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store i64 0, i64* %l4, align 8
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%c = getelementptr %struct.S, %struct.S* %p, i64 0, i32 1
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store i8 0, i8* %c, align 8
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%s = getelementptr %struct.S, %struct.S* %p, i64 0, i32 2
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store i16 0, i16* %s, align 2
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%i = getelementptr %struct.S, %struct.S* %p, i64 0, i32 3
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store i32 0, i32* %i, align 4
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ret void
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}
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define void @bar(%struct.S* %p) {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 4, 2
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; CHECK-NEXT: stw 4, 12(3)
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; CHECK-NEXT: sth 4, 10(3)
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; CHECK-NEXT: std 4, 0(3)
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; CHECK-NEXT: stb 4, 8(3)
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; CHECK-NEXT: blr
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%i = getelementptr %struct.S, %struct.S* %p, i64 0, i32 3
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store i32 2, i32* %i, align 4
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%s = getelementptr %struct.S, %struct.S* %p, i64 0, i32 2
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store i16 2, i16* %s, align 2
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%c = getelementptr %struct.S, %struct.S* %p, i64 0, i32 1
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store i8 2, i8* %c, align 8
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%l4 = bitcast %struct.S* %p to i64*
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store i64 2, i64* %l4, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @setSmallNeg() {
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; CHECK-LABEL: setSmallNeg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC1@toc@ha
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; CHECK-NEXT: addis 5, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 6, 2, .LC3@toc@ha
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; CHECK-NEXT: li 7, -7
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: ld 4, .LC1@toc@l(4)
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; CHECK-NEXT: ld 5, .LC2@toc@l(5)
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; CHECK-NEXT: ld 6, .LC3@toc@l(6)
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; CHECK-NEXT: stb 7, 0(3)
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; CHECK-NEXT: sth 7, 0(4)
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; CHECK-NEXT: std 7, 0(6)
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; CHECK-NEXT: stw 7, 0(5)
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; CHECK-NEXT: blr
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entry:
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store i8 -7, i8* @CVal, align 1
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store i16 -7, i16* @SVal, align 2
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store i32 -7, i32* @IVal, align 4
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store i64 -7, i64* @LVal, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @setSmallPos() {
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; CHECK-LABEL: setSmallPos:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC1@toc@ha
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; CHECK-NEXT: addis 5, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 6, 2, .LC3@toc@ha
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; CHECK-NEXT: li 7, 8
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: ld 4, .LC1@toc@l(4)
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; CHECK-NEXT: ld 5, .LC2@toc@l(5)
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; CHECK-NEXT: ld 6, .LC3@toc@l(6)
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; CHECK-NEXT: stb 7, 0(3)
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; CHECK-NEXT: sth 7, 0(4)
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; CHECK-NEXT: std 7, 0(6)
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; CHECK-NEXT: stw 7, 0(5)
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; CHECK-NEXT: blr
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entry:
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store i8 8, i8* @CVal, align 1
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store i16 8, i16* @SVal, align 2
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store i32 8, i32* @IVal, align 4
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store i64 8, i64* @LVal, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @setMaxNeg() {
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; CHECK-LABEL: setMaxNeg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC1@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 5, 2, .LC3@toc@ha
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; CHECK-NEXT: li 6, -32768
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; CHECK-NEXT: ld 3, .LC1@toc@l(3)
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; CHECK-NEXT: ld 4, .LC2@toc@l(4)
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; CHECK-NEXT: ld 5, .LC3@toc@l(5)
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; CHECK-NEXT: sth 6, 0(3)
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; CHECK-NEXT: stw 6, 0(4)
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; CHECK-NEXT: std 6, 0(5)
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; CHECK-NEXT: blr
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entry:
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store i16 -32768, i16* @SVal, align 2
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store i32 -32768, i32* @IVal, align 4
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store i64 -32768, i64* @LVal, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @setMaxPos() {
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; CHECK-LABEL: setMaxPos:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC1@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 5, 2, .LC3@toc@ha
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; CHECK-NEXT: li 6, 32767
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; CHECK-NEXT: ld 3, .LC1@toc@l(3)
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; CHECK-NEXT: ld 4, .LC2@toc@l(4)
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; CHECK-NEXT: ld 5, .LC3@toc@l(5)
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; CHECK-NEXT: sth 6, 0(3)
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; CHECK-NEXT: stw 6, 0(4)
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; CHECK-NEXT: std 6, 0(5)
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; CHECK-NEXT: blr
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entry:
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store i16 32767, i16* @SVal, align 2
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store i32 32767, i32* @IVal, align 4
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store i64 32767, i64* @LVal, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @setExcessiveNeg() {
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; CHECK-LABEL: setExcessiveNeg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC3@toc@ha
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; CHECK-NEXT: lis 5, -1
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; CHECK-NEXT: ld 3, .LC2@toc@l(3)
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; CHECK-NEXT: ld 4, .LC3@toc@l(4)
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; CHECK-NEXT: ori 5, 5, 32767
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; CHECK-NEXT: stw 5, 0(3)
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; CHECK-NEXT: std 5, 0(4)
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; CHECK-NEXT: blr
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entry:
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store i32 -32769, i32* @IVal, align 4
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store i64 -32769, i64* @LVal, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @setExcessivePos() {
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; CHECK-LABEL: setExcessivePos:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC4@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 5, 2, .LC3@toc@ha
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: ld 3, .LC4@toc@l(3)
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; CHECK-NEXT: ld 4, .LC2@toc@l(4)
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; CHECK-NEXT: ld 5, .LC3@toc@l(5)
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; CHECK-NEXT: ori 6, 6, 32768
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; CHECK-NEXT: sth 6, 0(3)
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; CHECK-NEXT: stw 6, 0(4)
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; CHECK-NEXT: std 6, 0(5)
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; CHECK-NEXT: blr
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entry:
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store i16 -32768, i16* @USVal, align 2
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store i32 32768, i32* @IVal, align 4
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store i64 32768, i64* @LVal, align 8
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ret void
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}
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define void @SetArr(i32 signext %Len) {
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; CHECK-LABEL: SetArr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cmpwi 3, 1
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; CHECK-NEXT: bltlr 0
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; CHECK-NEXT: # %bb.1: # %for.body.lr.ph
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; CHECK-NEXT: addis 4, 2, .LC5@toc@ha
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; CHECK-NEXT: addis 5, 2, .LC6@toc@ha
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; CHECK-NEXT: clrldi 6, 3, 32
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; CHECK-NEXT: ld 4, .LC5@toc@l(4)
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; CHECK-NEXT: ld 5, .LC6@toc@l(5)
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; CHECK-NEXT: ld 4, 0(4)
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; CHECK-NEXT: ld 5, 0(5)
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; CHECK-NEXT: mtctr 6
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; CHECK-NEXT: addi 3, 4, -8
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; CHECK-NEXT: addi 4, 5, -4
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; CHECK-NEXT: li 5, -7
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB8_2: # %for.body
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; CHECK-NEXT: #
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; CHECK-NEXT: stdu 5, 8(3)
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; CHECK-NEXT: stwu 5, 4(4)
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; CHECK-NEXT: bdnz .LBB8_2
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; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
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; CHECK-NEXT: blr
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entry:
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%cmp7 = icmp sgt i32 %Len, 0
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br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%0 = load i64*, i64** @arr, align 8
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%1 = load i32*, i32** @arri, align 8
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%wide.trip.count = zext i32 %Len to i64
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.lr.ph
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%indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i64, i64* %0, i64 %indvars.iv
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store i64 -7, i64* %arrayidx, align 8
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%arrayidx2 = getelementptr inbounds i32, i32* %1, i64 %indvars.iv
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store i32 -7, i32* %arrayidx2, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define void @setSameValDiffSizeCI() {
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; CHECK-LABEL: setSameValDiffSizeCI:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC0@toc@ha
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; CHECK-NEXT: li 5, 255
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; CHECK-NEXT: ld 3, .LC2@toc@l(3)
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; CHECK-NEXT: ld 4, .LC0@toc@l(4)
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; CHECK-NEXT: stw 5, 0(3)
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; CHECK-NEXT: stb 5, 0(4)
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; CHECK-NEXT: blr
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entry:
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store i32 255, i32* @IVal, align 4
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store i8 -1, i8* @CVal, align 1
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ret void
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}
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define void @setSameValDiffSizeSI() {
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; CHECK-LABEL: setSameValDiffSizeSI:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC2@toc@ha
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; CHECK-NEXT: addis 4, 2, .LC1@toc@ha
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: ld 3, .LC2@toc@l(3)
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; CHECK-NEXT: ld 4, .LC1@toc@l(4)
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; CHECK-NEXT: ori 5, 5, 65535
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; CHECK-NEXT: stw 5, 0(3)
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; CHECK-NEXT: sth 5, 0(4)
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; CHECK-NEXT: blr
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entry:
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store i32 65535, i32* @IVal, align 4
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store i16 -1, i16* @SVal, align 2
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ret void
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}
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