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04b8e84be8
In https://reviews.llvm.org/D92789 PPC64 checks were added that disallowed most VSX pattern matching. We enable some safe ones for 32bit in this patch. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D97503
144 lines
5.2 KiB
LLVM
144 lines
5.2 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \
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; RUN: -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 \
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; RUN: -verify-machineinstrs -vec-extabi | \
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; RUN: FileCheck %s --check-prefixes=AIX,AIX64
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; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 \
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; RUN: -verify-machineinstrs -vec-extabi | \
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; RUN: FileCheck %s --check-prefixes=AIX,AIX32
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define dso_local void @test(i32* %Arr, i32 signext %Len) {
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; CHECK-LABEL: test:
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; CHECK: lxvx [[REG:vs[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NOT: [[REG]]
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; CHECK: xxbrw vs{{[0-9]+}}, [[REG]]
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; AIX-LABEL: test:
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; AIX64: lxvx [[REG64:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
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; AIX32: lxv [[REG32:[0-9]+]], {{[0-9]+}}({{[0-9]+}})
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; AIX64-NOT: [[REG64]]
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; AIX64: xxbrw {{[0-9]+}}, [[REG64]]
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; AIX32: xxbrw {{[0-9]+}}, [[REG32]]
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entry:
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%cmp1 = icmp slt i32 0, %Len
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br i1 %cmp1, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%min.iters.check = icmp ult i32 %Len, 4
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br i1 %min.iters.check, label %scalar.ph, label %vector.ph
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vector.ph: ; preds = %for.body.lr.ph
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%n.mod.vf = urem i32 %Len, 4
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%n.vec = sub i32 %Len, %n.mod.vf
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0
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%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%induction = add <4 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3>
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%0 = add i32 %index, 0
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%1 = sext i32 %0 to i64
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%2 = getelementptr inbounds i32, i32* %Arr, i64 %1
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%3 = getelementptr inbounds i32, i32* %2, i32 0
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%4 = bitcast i32* %3 to <4 x i32>*
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%wide.load = load <4 x i32>, <4 x i32>* %4, align 4
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%5 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %wide.load)
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%6 = sext i32 %0 to i64
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%7 = getelementptr inbounds i32, i32* %Arr, i64 %6
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%8 = getelementptr inbounds i32, i32* %7, i32 0
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%9 = bitcast i32* %8 to <4 x i32>*
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store <4 x i32> %5, <4 x i32>* %9, align 4
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%index.next = add i32 %index, 4
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%10 = icmp eq i32 %index.next, %n.vec
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br i1 %10, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i32 %Len, %n.vec
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br i1 %cmp.n, label %for.cond.for.cond.cleanup_crit_edge, label %scalar.ph
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scalar.ph: ; preds = %middle.block, %for.body.lr.ph
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%bc.resume.val = phi i32 [ %n.vec, %middle.block ], [ 0, %for.body.lr.ph ]
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br label %for.body
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for.cond.for.cond.cleanup_crit_edge: ; preds = %middle.block, %for.inc
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.for.cond.cleanup_crit_edge, %entry
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br label %for.end
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for.body: ; preds = %for.inc, %scalar.ph
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%i.02 = phi i32 [ %bc.resume.val, %scalar.ph ], [ %inc, %for.inc ]
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%idxprom = sext i32 %i.02 to i64
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%arrayidx = getelementptr inbounds i32, i32* %Arr, i64 %idxprom
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%11 = load i32, i32* %arrayidx, align 4
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%12 = call i32 @llvm.bswap.i32(i32 %11)
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%idxprom1 = sext i32 %i.02 to i64
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%arrayidx2 = getelementptr inbounds i32, i32* %Arr, i64 %idxprom1
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store i32 %12, i32* %arrayidx2, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%inc = add nsw i32 %i.02, 1
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%cmp = icmp slt i32 %inc, %Len
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br i1 %cmp, label %for.body, label %for.cond.for.cond.cleanup_crit_edge
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for.end: ; preds = %for.cond.cleanup
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ret void
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}
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define dso_local <8 x i16> @test_halfword(<8 x i16> %a) local_unnamed_addr {
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; CHECK-LABEL: test_halfword:
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; CHECK: xxbrh vs34, vs34
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; CHECK-NEXT: blr
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; AIX-LABEL: test_halfword:
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; AIX: xxbrh 34, 34
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; AIX-NEXT: blr
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entry:
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%0 = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %a)
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ret <8 x i16> %0
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}
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define dso_local <2 x i64> @test_doubleword(<2 x i64> %a) local_unnamed_addr {
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; CHECK-LABEL: test_doubleword:
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; CHECK: xxbrd vs34, vs34
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; CHECK-NEXT: blr
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; AIX-LABEL: test_doubleword:
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; AIX: xxbrd 34, 34
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; AIX-NEXT: blr
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entry:
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%0 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
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ret <2 x i64> %0
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}
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define dso_local <1 x i128> @test_quadword(<1 x i128> %a) local_unnamed_addr {
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; CHECK-LABEL: test_quadword:
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; CHECK: xxbrq vs34, vs34
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; CHECK-NEXT: blr
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; AIX-LABEL: test_quadword:
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; AIX: xxbrq 34, 34
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; AIX-NEXT: blr
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entry:
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%0 = call <1 x i128> @llvm.bswap.v1i128(<1 x i128> %a)
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ret <1 x i128> %0
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <1 x i128> @llvm.bswap.v1i128(<1 x i128>)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare i32 @llvm.bswap.i32(i32)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
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