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On little endian targets prior to Power9, we spill vector registers using a swapping store (i.e. stdxvd2x saves the vector with the two doublewords in big endian order regardless of endianness). This is generally not a problem since we restore them using the corresponding swapping load (lxvd2x). However if the restore is done by the unwinder, the vector register contains data in the incorrect order. This patch fixes that by using Altivec loads/stores for vector saves and restores in PEI (which keep the order correct) under those specific conditions: - EH aware function - Subtarget requires swaps for VSX memops (Little Endian prior to Power9) Differential revision: https://reviews.llvm.org/D73692
68 lines
2.9 KiB
LLVM
68 lines
2.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-PWR9 %s
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define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: testSpill:
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; CHECK-DAG: li [[REG48:[0-9]+]], 48
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; CHECK-DAG: li [[REG64:[0-9]+]], 64
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; CHECK-DAG: li [[REG80:[0-9]+]], 80
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; CHECK-DAG: li [[REG96:[0-9]+]], 96
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; CHECK-DAG: stvx 28, 1, [[REG48]] # 16-byte Folded Spill
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; CHECK-DAG: stvx 29, 1, [[REG64]] # 16-byte Folded Spill
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; CHECK-DAG: stvx 30, 1, [[REG80]] # 16-byte Folded Spill
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; CHECK-DAG: stvx 31, 1, [[REG96]] # 16-byte Folded Spill
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; CHECK: .LBB0_3
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; CHECK-DAG: li [[REG96_LD:[0-9]+]], 96
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; CHECK-DAG: li [[REG80_LD:[0-9]+]], 80
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; CHECK-DAG: li [[REG64_LD:[0-9]+]], 64
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; CHECK-DAG: li [[REG48_LD:[0-9]+]], 48
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; CHECK-DAG: lvx 31, 1, [[REG96_LD]] # 16-byte Folded Reload
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; CHECK-DAG: lvx 30, 1, [[REG80_LD]] # 16-byte Folded Reload
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; CHECK-DAG: lvx 29, 1, [[REG64_LD]] # 16-byte Folded Reload
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; CHECK-DAG: lvx 28, 1, [[REG48_LD]] # 16-byte Folded Reload
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; CHECK: mtlr 0
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; CHECK-NEXT: blr
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;
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; CHECK-PWR9-LABEL: testSpill:
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; CHECK-PWR9-DAG: stxv 62, 64(1) # 16-byte Folded Spill
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; CHECK-PWR9-DAG: stxv 63, 80(1) # 16-byte Folded Spill
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; CHECK-PWR9-DAG: stxv 60, 32(1) # 16-byte Folded Spill
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; CHECK-PWR9-DAG: stxv 61, 48(1) # 16-byte Folded Spill
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; CHECK-PWR9-NOT: NOT
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; CHECK-PWR9-DAG: lxv 63, 80(1) # 16-byte Folded Reload
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; CHECK-PWR9-DAG: lxv 62, 64(1) # 16-byte Folded Reload
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; CHECK-PWR9-DAG: lxv 61, 48(1) # 16-byte Folded Reload
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; CHECK-PWR9-DAG: lxv 60, 32(1) # 16-byte Folded Reload
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; CHECK-PWR9: mtlr 0
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; CHECK-PWR9-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)
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%tobool = icmp eq i32 %0, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%call = tail call <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b)
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br label %if.end
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if.else: ; preds = %entry
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%call1 = tail call <4 x i32> @test2(<4 x i32> %b, <4 x i32> %a)
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%c.0.in = phi <4 x i32> [ %call, %if.then ], [ %call1, %if.else ]
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%call3 = tail call <4 x i32> @test1(<4 x i32> %b, <4 x i32> %a)
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%call5 = tail call <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b)
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%add4 = add <4 x i32> %a, <i32 0, i32 0, i32 2, i32 2>
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%add6 = add <4 x i32> %add4, %c.0.in
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%c.0 = add <4 x i32> %add6, %call3
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%add7 = add <4 x i32> %c.0, %call5
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ret <4 x i32> %add7
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
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declare <4 x i32> @test1(<4 x i32>, <4 x i32>)
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declare <4 x i32> @test2(<4 x i32>, <4 x i32>)
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