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e1cb504775
This is an enhancement to D77895 to avoid another round-trip from XMM->GPR->XMM. This time we handle the case of starting/ending with an f64 and casting to signed i32 as the intermediate value. It's a bit more involved than I initially assumed because we need to use target-specific opcodes to represent the non-standard cast ops. Differential Revision: https://reviews.llvm.org/D78362
41 lines
1.4 KiB
LLVM
41 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
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define zeroext i8 @t(double %x) nounwind readnone {
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; CHECK-LABEL: t:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: cvttpd2dq %xmm0, %xmm1
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; CHECK-NEXT: cvtdq2pd %xmm1, %xmm1
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; CHECK-NEXT: cmpeqsd %xmm0, %xmm1
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; CHECK-NEXT: movd %xmm1, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retl
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entry:
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%0 = fptosi double %x to i32 ; <i32> [#uses=1]
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%1 = sitofp i32 %0 to double ; <double> [#uses=1]
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%2 = fcmp oeq double %1, %x ; <i1> [#uses=1]
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%retval12 = zext i1 %2 to i8 ; <i8> [#uses=1]
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ret i8 %retval12
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}
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define zeroext i8 @u(double %x) nounwind readnone {
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; CHECK-LABEL: u:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: cvttpd2dq %xmm0, %xmm1
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; CHECK-NEXT: cvtdq2pd %xmm1, %xmm1
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; CHECK-NEXT: cmpneqsd %xmm0, %xmm1
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; CHECK-NEXT: movd %xmm1, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retl
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entry:
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%0 = fptosi double %x to i32 ; <i32> [#uses=1]
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%1 = sitofp i32 %0 to double ; <double> [#uses=1]
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%2 = fcmp une double %1, %x ; <i1> [#uses=1]
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%retval12 = zext i1 %2 to i8 ; <i8> [#uses=1]
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ret i8 %retval12
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}
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