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https://github.com/RPCS3/llvm-mirror.git
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f11fad31d2
- Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
204 lines
6.2 KiB
C++
204 lines
6.2 KiB
C++
//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonRegisterInfo.h"
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#include "Hexagon.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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HexagonRegisterInfo::HexagonRegisterInfo()
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: HexagonGenRegisterInfo(Hexagon::R31) {}
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bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
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return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
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R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
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}
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bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const {
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return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
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}
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const MCPhysReg *
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HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF) const {
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static const MCPhysReg CallerSavedRegsV4[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
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Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
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Hexagon::R15, 0
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};
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auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
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switch (HST.getHexagonArchVersion()) {
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case HexagonSubtarget::V4:
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case HexagonSubtarget::V5:
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case HexagonSubtarget::V55:
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case HexagonSubtarget::V60:
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return CallerSavedRegsV4;
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}
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llvm_unreachable(
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"Callee saved registers requested for unknown archtecture version");
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}
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const MCPhysReg *
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HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const MCPhysReg CalleeSavedRegsV3[] = {
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Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
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Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
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};
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switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
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case HexagonSubtarget::V4:
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case HexagonSubtarget::V5:
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case HexagonSubtarget::V55:
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case HexagonSubtarget::V60:
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return CalleeSavedRegsV3;
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}
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llvm_unreachable("Callee saved registers requested for unknown architecture "
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"version");
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}
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BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
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const {
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BitVector Reserved(getNumRegs());
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Reserved.set(HEXAGON_RESERVED_REG_1);
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Reserved.set(HEXAGON_RESERVED_REG_2);
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Reserved.set(Hexagon::R29);
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Reserved.set(Hexagon::R30);
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Reserved.set(Hexagon::R31);
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Reserved.set(Hexagon::D14);
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Reserved.set(Hexagon::D15);
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Reserved.set(Hexagon::LC0);
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Reserved.set(Hexagon::LC1);
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Reserved.set(Hexagon::SA0);
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Reserved.set(Hexagon::SA1);
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return Reserved;
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}
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void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOp,
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RegScavenger *RS) const {
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//
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// Hexagon_TODO: Do we need to enforce this for Hexagon?
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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MachineBasicBlock &MB = *MI.getParent();
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MachineFunction &MF = *MB.getParent();
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auto &HST = MF.getSubtarget<HexagonSubtarget>();
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auto &HII = *HST.getInstrInfo();
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auto &HFI = *HST.getFrameLowering();
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unsigned BP = 0;
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int FI = MI.getOperand(FIOp).getIndex();
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// Select the base pointer (BP) and calculate the actual offset from BP
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// to the beginning of the object at index FI.
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int Offset = HFI.getFrameIndexReference(MF, FI, BP);
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// Add the offset from the instruction.
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int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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case Hexagon::TFR_FIA:
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MI.setDesc(HII.get(Hexagon::A2_addi));
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MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
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MI.RemoveOperand(FIOp+1);
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return;
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case Hexagon::TFR_FI:
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// Set up the instruction for updating below.
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MI.setDesc(HII.get(Hexagon::A2_addi));
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break;
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}
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if (HII.isValidOffset(Opc, RealOffset)) {
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MI.getOperand(FIOp).ChangeToRegister(BP, false);
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MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
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return;
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}
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#ifndef NDEBUG
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const Function *F = MF.getFunction();
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dbgs() << "In function ";
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if (F) dbgs() << F->getName();
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else dbgs() << "<?>";
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dbgs() << ", BB#" << MB.getNumber() << "\n" << MI;
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#endif
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llvm_unreachable("Unhandled instruction");
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}
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unsigned HexagonRegisterInfo::getRARegister() const {
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return Hexagon::R31;
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}
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unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
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&MF) const {
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const HexagonFrameLowering *TFI = getFrameLowering(MF);
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if (TFI->hasFP(MF))
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return getFrameRegister();
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return getStackRegister();
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}
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unsigned HexagonRegisterInfo::getFrameRegister() const {
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return Hexagon::R30;
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}
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unsigned HexagonRegisterInfo::getStackRegister() const {
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return Hexagon::R29;
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}
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bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
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const {
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return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
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}
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unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
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return Hexagon::R6;
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}
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#define GET_REGINFO_TARGET_DESC
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#include "HexagonGenRegisterInfo.inc"
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