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70 lines
1.7 KiB
C++
70 lines
1.7 KiB
C++
//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by AMDGPURegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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namespace AMDGPU {
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enum PartialMappingIdx {
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None = - 1,
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PM_SGPR32 = 0,
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PM_SGPR64 = 1,
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PM_VGPR32 = 2,
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PM_VGPR64 = 3,
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PM_SGPR1 = 4,
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PM_VGPR1 = 5,
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};
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const RegisterBankInfo::PartialMapping PartMappings[] {
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// StartIdx, Length, RegBank
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{0, 32, SGPRRegBank},
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{0, 64, SGPRRegBank},
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{0, 32, VGPRRegBank},
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{0, 64, VGPRRegBank},
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{0, 1, SCCRegBank},
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{0, 1, SGPRRegBank}
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};
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const RegisterBankInfo::ValueMapping ValMappings[] {
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// SGPR 32-bit
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{&PartMappings[0], 1},
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// SGPR 64-bit
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{&PartMappings[1], 1},
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// VGPR 32-bit
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{&PartMappings[2], 1},
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// VGPR 64-bit
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{&PartMappings[3], 1},
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{&PartMappings[4], 1},
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{&PartMappings[5], 1}
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};
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enum ValueMappingIdx {
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SGPRStartIdx = 0,
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VGPRStartIdx = 2
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};
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const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
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unsigned Size) {
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unsigned Idx;
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if (Size == 1) {
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Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
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} else {
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assert(Size % 32 == 0);
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Idx = BankID == AMDGPU::SGPRRegBankID ? SGPRStartIdx : VGPRStartIdx;
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Idx += (Size / 32) - 1;
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}
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return &ValMappings[Idx];
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}
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} // End AMDGPU namespace.
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} // End llvm namespace.
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