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d2e6077460
`llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309755
94 lines
3.6 KiB
LLVM
94 lines
3.6 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -show-mc-encoding | FileCheck %s
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define void @coproc(i8* %i) nounwind {
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entry:
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; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
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%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
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; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: cdp p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: cdp2 p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: ldc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
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%2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
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; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
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%3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind
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ret void
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}
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define hidden void @cond_cdp(i32 %a) {
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; CHECK-LABEL: cond_cdp:
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entry:
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%tobool = icmp eq i32 %a, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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; CHECK: it ne
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; CHECK: cdpne p15, #0, c0, c0, c0, #0 @ encoding: [0x00,0xee,0x00,0x0f]
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tail call void @llvm.arm.cdp(i32 15, i32 0, i32 0, i32 0, i32 0, i32 0)
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br label %if.end
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if.end:
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ret void
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}
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declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc(i32, i32, i8*) nounwind
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declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
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declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
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declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind
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