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6a7de7e3ad
Summary: ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort. We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code. Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one. The test pr34381.ll had to have fast-isel removed because it was relying on a fast isel abort to hit the bug. The test case still seems valid with fast-isel disabled though some of the instructions changed. Reviewers: spatel, zvi, igorb, guyblank, RKSimon Reviewed By: guyblank Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37320 llvm-svn: 312422
84 lines
2.8 KiB
LLVM
84 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -fast-isel-abort=1 -o - %s | FileCheck %s -check-prefix=X64
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@var_825 = external global i16, align 2
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@var_32 = external global i16, align 2
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@var_901 = external global i16, align 2
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@var_826 = external global i64, align 8
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@var_57 = external global i64, align 8
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@var_900 = external global i16, align 2
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@var_28 = external constant i64, align 8
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@var_827 = external global i16, align 2
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define void @foo() {
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; X64-LABEL: foo:
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; X64: # BB#0: # %entry
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: movl %eax, %ecx
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; X64-NEXT: movabsq $-1142377792914660288, %rdx # imm = 0xF02575732E06E440
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; X64-NEXT: movw $0, var_825
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; X64-NEXT: movzwl var_32, %eax
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; X64-NEXT: movzwl var_901, %esi
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; X64-NEXT: movl %eax, %edi
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; X64-NEXT: xorl %esi, %edi
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; X64-NEXT: movl %eax, %esi
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; X64-NEXT: xorl %edi, %esi
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; X64-NEXT: addl %eax, %esi
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; X64-NEXT: movslq %esi, %r8
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; X64-NEXT: movq %r8, var_826
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; X64-NEXT: movzwl var_32, %eax
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; X64-NEXT: movl %eax, %r8d
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; X64-NEXT: movzwl var_901, %eax
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; X64-NEXT: xorl $51981, %eax # imm = 0xCB0D
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; X64-NEXT: movslq %eax, %r9
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; X64-NEXT: xorq %rdx, %r9
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; X64-NEXT: movq %r8, %rdx
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; X64-NEXT: xorq %r9, %rdx
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; X64-NEXT: xorq $-1, %rdx
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; X64-NEXT: xorq %rdx, %r8
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; X64-NEXT: movq %r8, %rdx
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; X64-NEXT: orq var_57, %rdx
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; X64-NEXT: orq %rdx, %r8
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; X64-NEXT: movw %r8w, %r10w
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; X64-NEXT: movw %r10w, var_900
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; X64-NEXT: cmpq var_28, %rcx
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; X64-NEXT: setne %r11b
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; X64-NEXT: andb $1, %r11b
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; X64-NEXT: movzbl %r11b, %eax
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; X64-NEXT: movw %ax, %r10w
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; X64-NEXT: movw %r10w, var_827
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; X64-NEXT: retq
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entry:
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store i16 0, i16* @var_825, align 2
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%v0 = load i16, i16* @var_32, align 2
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%conv = zext i16 %v0 to i32
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%v2 = load i16, i16* @var_901, align 2
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%conv2 = zext i16 %v2 to i32
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%xor = xor i32 %conv, %conv2
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%xor3 = xor i32 %conv, %xor
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%add = add nsw i32 %xor3, %conv
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%conv5 = sext i32 %add to i64
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store i64 %conv5, i64* @var_826, align 8
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%v4 = load i16, i16* @var_32, align 2
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%conv6 = zext i16 %v4 to i64
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%v6 = load i16, i16* @var_901, align 2
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%conv8 = zext i16 %v6 to i32
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%xor9 = xor i32 51981, %conv8
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%conv10 = sext i32 %xor9 to i64
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%xor11 = xor i64 -1142377792914660288, %conv10
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%xor12 = xor i64 %conv6, %xor11
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%neg = xor i64 %xor12, -1
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%xor13 = xor i64 %conv6, %neg
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%v9 = load i16, i16* @var_901, align 2
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%v10 = load i64, i64* @var_57, align 8
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%or = or i64 %xor13, %v10
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%or23 = or i64 %xor13, %or
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%conv24 = trunc i64 %or23 to i16
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store i16 %conv24, i16* @var_900, align 2
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%v11 = load i64, i64* @var_28, align 8
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%cmp = icmp ne i64 0, %v11
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%conv25 = zext i1 %cmp to i16
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store i16 %conv25, i16* @var_827, align 2
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ret void
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}
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