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4e4ba838d9
Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
50 lines
1.2 KiB
YAML
50 lines
1.2 KiB
YAML
# RUN: llc -mtriple=i386-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s
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---
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# CHECK-LABEL: name: func0
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name: func0
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42
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; CHECK: %ebp = COPY killed [[REG0]]
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%0 : gr32 = MOV32ri 42
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%ebp = COPY %0
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...
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---
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# CHECK-LABEL: name: func2
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-NOT: %eax = MOV32ri 42
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; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42
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; CHECK: %ebp = COPY killed [[REG0]]
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%eax = MOV32ri 13
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%0 : gr32 = MOV32ri 42
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%ebp = COPY %0
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; CHECK: [[REG1:%e[a-z]+]] = MOV32ri 23
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; CHECK: [[REG2:%e[a-z]+]] = MOV32ri 7
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; CHECK: [[REG1]] = ADD32ri8 [[REG1]], 5, implicit-def dead %eflags
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%1 : gr32 = MOV32ri 23
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%2 : gr32 = MOV32ri 7
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%1 = ADD32ri8 %1, 5, implicit-def dead %eflags
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NOOP implicit %ebp
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; CHECK: NOOP implicit killed [[REG2]]
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; CHECK: NOOP implicit killed [[REG1]]
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NOOP implicit %2
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NOOP implicit %1
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RETQ %eax
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...
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---
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# CHECK-LABEL: name: func3
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name: func3
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK dead {{%e[a-z]+}} = MOV32ri 42
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dead %0 : gr32 = MOV32ri 42
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...
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