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a12a4b963e
Summary: LiveRangeShrink pass moves instruction right after the definition with the same BB if the instruction and its operands all have more than one use. This pass is inexpensive and guarantees optimal live-range within BB. Reviewers: davidxl, wmi, hfinkel, MatzeB, andreadb Reviewed By: MatzeB, andreadb Subscribers: hiraditya, jyknight, sanjoy, skatkov, gberry, jholewinski, qcolombet, javed.absar, krytarowski, atrick, spatel, RKSimon, andreadb, MatzeB, mehdi_amini, mgorny, efriedma, davide, dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D32563 llvm-svn: 304371
48 lines
1.8 KiB
LLVM
48 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;
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; PR30298: Check if the target doesn't have SSE2, compiler will not crash
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; or generate incorrect code because of vector mul width shrinking optimization.
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;
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; RUN: llc -mtriple=i386-pc-linux-gnu -mattr=+sse < %s | FileCheck %s
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@c = external global i32*, align 8
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define void @mul_2xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64 %index) nounwind {
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; CHECK-LABEL: mul_2xi8:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl c, %esi
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; CHECK-NEXT: movzbl 1(%edx,%ecx), %edi
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; CHECK-NEXT: movzbl (%edx,%ecx), %edx
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; CHECK-NEXT: movzbl 1(%eax,%ecx), %ebx
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; CHECK-NEXT: imull %edi, %ebx
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; CHECK-NEXT: movzbl (%eax,%ecx), %eax
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; CHECK-NEXT: imull %edx, %eax
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; CHECK-NEXT: movl %ebx, 4(%esi,%ecx,4)
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; CHECK-NEXT: movl %eax, (%esi,%ecx,4)
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: retl
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entry:
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%pre = load i32*, i32** @c
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%tmp6 = getelementptr inbounds i8, i8* %a, i64 %index
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%tmp7 = bitcast i8* %tmp6 to <2 x i8>*
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%wide.load = load <2 x i8>, <2 x i8>* %tmp7, align 1
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%tmp8 = zext <2 x i8> %wide.load to <2 x i32>
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%tmp10 = getelementptr inbounds i8, i8* %b, i64 %index
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%tmp11 = bitcast i8* %tmp10 to <2 x i8>*
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%wide.load17 = load <2 x i8>, <2 x i8>* %tmp11, align 1
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%tmp12 = zext <2 x i8> %wide.load17 to <2 x i32>
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%tmp13 = mul nuw nsw <2 x i32> %tmp12, %tmp8
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%tmp14 = getelementptr inbounds i32, i32* %pre, i64 %index
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%tmp15 = bitcast i32* %tmp14 to <2 x i32>*
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store <2 x i32> %tmp13, <2 x i32>* %tmp15, align 4
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ret void
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}
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