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4d7130da2e
This change implements the following vector operations:
- Vector Compare Not Equal
- vcmpneb(.) vcmpneh(.) vcmpnew(.)
- vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
- Vector Extract Unsigned
- vextractub vextractuh vextractuw vextractd
- vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
- Vector Insert
- vinsertb vinserth vinsertw vinsertd
26 instructions.
Phabricator: http://reviews.llvm.org/D15916
llvm-svn: 262392
119 lines
4.8 KiB
Plaintext
119 lines
4.8 KiB
Plaintext
//===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
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TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
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Altivec:
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- Vector Compare Not Equal (Zero):
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vcmpneb(.) vcmpneh(.) vcmpnew(.)
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vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
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. Same as other VCMP*, use VCMP/VCMPo form (support intrinsic)
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- Vector Extract Unsigned: vextractub vextractuh vextractuw vextractd
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. Don't use llvm extractelement because they have different semantics
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. Use instrinstics:
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(set v2i64:$vD, (int_ppc_altivec_vextractub v16i8:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractuh v8i16:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractuw v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractd v2i64:$vA, imm:$UIMM))
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- Vector Extract Unsigned Byte Left/Right-Indexed:
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vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
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. Use instrinstics:
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// Left-Indexed
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(set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
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// Right-Indexed
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(set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
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- Vector Insert Element Instructions: vinsertb vinsertd vinserth vinsertw
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(set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
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(set v8i16:$vD, (int_ppc_altivec_vinsertd v8i16:$vA, imm:$UIMM))
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(set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vinsertw v2i64:$vA, imm:$UIMM))
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VSX:
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- QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
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. ref: XSCMPUDP
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def XSCMPUDP : XX3Form_1<60, 35,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
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. No SDAG, intrinsic, builtin are required??
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Or llvm fcmp order/unorder compare??
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- DP/QP Compare Exponents: xscmpexpdp xscmpexpqp
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. No SDAG, intrinsic, builtin are required?
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- DP Compare ==, >=, >, !=: xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
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. I checked existing instruction "XSCMPUDP". They are different in target
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register. "XSCMPUDP" write to CR field, xscmp*dp write to VSX register
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. Use instrinsic:
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(set i128:$XT, (int_ppc_vsx_xscmpeqdp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpgedp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpgtdp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpnedp f64:$XA, f64:$XB))
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- Vector Compare Not Equal: xvcmpnedp xvcmpnedp. xvcmpnesp xvcmpnesp.
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. Similar to xvcmpeqdp:
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defm XVCMPEQDP : XX3Form_Rcr<60, 99,
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"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
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int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
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. So we should use "XX3Form_Rcr" to implement instrinsic
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- Convert DP -> QP: xscvdpqp
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. Similar to XSCVDPSP:
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def XSCVDPSP : XX2Form<60, 265,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsp $XT, $XB", IIC_VecFP, []>;
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. So, No SDAG, intrinsic, builtin are required??
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- Round & Convert QP -> DP (dword[1] is set to zero): xscvqpdp xscvqpdpo
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. Similar to XSCVDPSP
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. No SDAG, intrinsic, builtin are required??
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- Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero):
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xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz
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. According to PowerISA_V3.0, these are similar to "XSCVDPSXDS", "XSCVDPSXWS",
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"XSCVDPUXDS", "XSCVDPUXWS"
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. DAG patterns:
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(set f128:$XT, (PPCfctidz f128:$XB)) // xscvqpsdz
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(set f128:$XT, (PPCfctiwz f128:$XB)) // xscvqpswz
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(set f128:$XT, (PPCfctiduz f128:$XB)) // xscvqpudz
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(set f128:$XT, (PPCfctiwuz f128:$XB)) // xscvqpuwz
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- Convert (Un)Signed DWord -> QP: xscvsdqp xscvudqp
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. Similar to XSCVSXDSP
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. (set f128:$XT, (PPCfcfids f64:$XB)) // xscvsdqp
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(set f128:$XT, (PPCfcfidus f64:$XB)) // xscvudqp
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- (Round &) Convert DP <-> HP: xscvdphp xscvhpdp
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. Similar to XSCVDPSP
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. No SDAG, intrinsic, builtin are required??
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- Vector HP -> SP: xvcvhpsp xvcvsphp
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. Similar to XVCVDPSP:
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def XVCVDPSP : XX2Form<60, 393,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
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. No SDAG, intrinsic, builtin are required??
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- Round to Quad-Precision Integer: xsrqpi xsrqpix
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. These are combination of "XSRDPI", "XSRDPIC", "XSRDPIM", .., because you
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need to assign rounding mode in instruction
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. Provide builtin?
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(set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB))
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(set f128:$vT, (int_ppc_vsx_xsrqpix f128:$vB))
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- Round Quad-Precision to Double-Extended Precision (fp80): xsrqpxp
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. Provide builtin?
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(set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB))
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