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f8a414589e
Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
148 lines
5.0 KiB
C++
148 lines
5.0 KiB
C++
//===- LiveRegUnits.cpp - Register Unit Set -------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file imlements the LiveRegUnits set.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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using namespace llvm;
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void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
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for (unsigned U = 0, E = TRI->getNumRegUnits(); U != E; ++U) {
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for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
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if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
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Units.reset(U);
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}
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}
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}
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void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
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for (unsigned U = 0, E = TRI->getNumRegUnits(); U != E; ++U) {
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for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
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if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
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Units.set(U);
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}
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}
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}
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void LiveRegUnits::stepBackward(const MachineInstr &MI) {
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// Remove defined registers and regmask kills from the set.
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (O->isReg()) {
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if (!O->isDef() || O->isDebug())
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continue;
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Register Reg = O->getReg();
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if (!Register::isPhysicalRegister(Reg))
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continue;
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removeReg(Reg);
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} else if (O->isRegMask())
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removeRegsNotPreserved(O->getRegMask());
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}
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// Add uses to the set.
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (!O->isReg() || !O->readsReg() || O->isDebug())
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continue;
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Register Reg = O->getReg();
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if (!Register::isPhysicalRegister(Reg))
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continue;
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addReg(Reg);
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}
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}
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void LiveRegUnits::accumulate(const MachineInstr &MI) {
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// Add defs, uses and regmask clobbers to the set.
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (O->isReg()) {
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Register Reg = O->getReg();
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if (!Register::isPhysicalRegister(Reg))
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continue;
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if (!O->isDef() && !O->readsReg())
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continue;
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addReg(Reg);
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} else if (O->isRegMask())
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addRegsInMask(O->getRegMask());
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}
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}
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/// Add live-in registers of basic block \p MBB to \p LiveUnits.
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static void addBlockLiveIns(LiveRegUnits &LiveUnits,
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const MachineBasicBlock &MBB) {
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for (const auto &LI : MBB.liveins())
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LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
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}
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/// Adds all callee saved registers to \p LiveUnits.
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static void addCalleeSavedRegs(LiveRegUnits &LiveUnits,
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const MachineFunction &MF) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
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LiveUnits.addReg(*CSR);
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}
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void LiveRegUnits::addPristines(const MachineFunction &MF) {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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if (!MFI.isCalleeSavedInfoValid())
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return;
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/// This function will usually be called on an empty object, handle this
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/// as a special case.
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if (empty()) {
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/// Add all callee saved regs, then remove the ones that are saved and
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/// restored.
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addCalleeSavedRegs(*this, MF);
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/// Remove the ones that are not saved/restored; they are pristine.
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for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
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removeReg(Info.getReg());
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return;
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}
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/// If a callee-saved register that is not pristine is already present
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/// in the set, we should make sure that it stays in it. Precompute the
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/// set of pristine registers in a separate object.
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/// Add all callee saved regs, then remove the ones that are saved+restored.
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LiveRegUnits Pristine(*TRI);
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addCalleeSavedRegs(Pristine, MF);
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/// Remove the ones that are not saved/restored; they are pristine.
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for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
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Pristine.removeReg(Info.getReg());
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addUnits(Pristine.getBitVector());
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}
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void LiveRegUnits::addLiveOuts(const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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addPristines(MF);
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// To get the live-outs we simply merge the live-ins of all successors.
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for (const MachineBasicBlock *Succ : MBB.successors())
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addBlockLiveIns(*this, *Succ);
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// For the return block: Add all callee saved registers.
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if (MBB.isReturnBlock()) {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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if (MFI.isCalleeSavedInfoValid())
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addCalleeSavedRegs(*this, MF);
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}
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}
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void LiveRegUnits::addLiveIns(const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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addPristines(MF);
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addBlockLiveIns(*this, MBB);
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}
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