Simon Pilgrim d3e938c0f5 [X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions ... The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes. Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases. Differential Revision: http://reviews.llvm.org/D8690 llvm-svn: 248878		2015-09-30 08:17:50 +00:00
..
AArch64	Fix test from r248825.	2015-09-29 20:50:15 +00:00
AMDGPU	AMDGPU: Fix splitting x16 SMRD loads	2015-09-28 20:54:52 +00:00
ARM	[ARM] Don't generate clrex for pre-v7 targets.	2015-09-26 00:14:02 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips
MIR
MSP430
NVPTX
PowerPC	[DAGCombine] Fix getStoreMergeAndAliasCandidates's AA-enabled chain walking	2015-09-28 08:02:14 +00:00
SPARC
SystemZ	[SystemZ] Fix expansion of ISD::FPOW and ISD::FSINCOS	2015-09-21 17:35:45 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Rename test files to match platform naming conventions.	2015-09-29 08:13:58 +00:00
WinEH	[WinEH] Teach AsmPrinter about funclets	2015-09-29 20:12:33 +00:00
X86	[X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions	2015-09-30 08:17:50 +00:00
XCore