Scott Linder 3a0c436c93 [AMDGPU] Fix PC register mapping in wave32 mode ...

Summary:
The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76732

2020-03-26 14:43:25 -04:00

..

AMDGPU

[AMDGPU] Fix PC register mapping in wave32 mode

2020-03-26 14:43:25 -04:00

CMakeLists.txt

Add AMDGPU MC unittests only when AMDGPU target is being built

2020-03-23 12:11:07 -04:00

Disassembler.cpp

[X86][Disassembler] Fix a bug when disassembling an empty string

2020-01-13 10:42:21 -08:00

DwarfLineTables.cpp

[Mips] Use appropriate private label prefix based on Mips ABI

2019-10-23 12:24:35 +02:00

MCInstPrinter.cpp

[Mips] Use appropriate private label prefix based on Mips ABI

2019-10-23 12:24:35 +02:00

StringTableBuilderTest.cpp

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00

TargetRegistry.cpp

Update the file headers across all of the LLVM projects in the monorepo

2019-01-19 08:50:56 +00:00