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23c462a8b5
This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun llvm-svn: 363757
36 lines
1.7 KiB
LLVM
36 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS
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; Test that the correct ISA version of the unaligned memory operations is
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; selected up front.
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define void @g2(i32* %a, i32* %b) {
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; MIPS-LABEL: name: g2
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; MIPS: bb.0.entry:
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; MIPS: liveins: $a0, $a1
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; MIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; MIPS: [[LWL:%[0-9]+]]:gpr32 = LWL [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1)
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; MIPS: [[LWR:%[0-9]+]]:gpr32 = LWR [[COPY1]], 3, [[LWL]] :: (load 4 from %ir.a, align 1)
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; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store 4 into %ir.b, align 1)
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; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store 4 into %ir.b, align 1)
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; MIPS: RetRA
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; MICROMIPS-LABEL: name: g2
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; MICROMIPS: bb.0.entry:
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; MICROMIPS: liveins: $a0, $a1
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; MICROMIPS: [[COPY:%[0-9]+]]:gpr32 = COPY $a1
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; MICROMIPS: [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
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; MICROMIPS: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; MICROMIPS: [[LWL_MM:%[0-9]+]]:gpr32 = LWL_MM [[COPY1]], 0, [[DEF]] :: (load 4 from %ir.a, align 1)
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; MICROMIPS: [[LWR_MM:%[0-9]+]]:gpr32 = LWR_MM [[COPY1]], 3, [[LWL_MM]] :: (load 4 from %ir.a, align 1)
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; MICROMIPS: SWL_MM [[LWR_MM]], [[COPY]], 0 :: (store 4 into %ir.b, align 1)
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; MICROMIPS: SWR_MM [[LWR_MM]], [[COPY]], 3 :: (store 4 into %ir.b, align 1)
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; MICROMIPS: RetRA
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entry:
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%0 = load i32, i32* %a, align 1
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store i32 %0, i32* %b, align 1
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ret void
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}
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