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84 lines
3.6 KiB
Plaintext
84 lines
3.6 KiB
Plaintext
Code Generation Notes for MSA
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=============================
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Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
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optimisation, reduce the size of the ISel matcher, and reduce repetition in
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the implementation. In a small number of cases, this can cause different
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(semantically equivalent) instructions to be used in place of the requested
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instruction, even when no optimisation has taken place.
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Instructions
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============
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This section describes any quirks of instruction selection for MSA. For
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example, two instructions might be equally valid for some given IR and one is
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chosen in preference to the other.
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bclri.b:
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It is not possible to emit bclri.b since andi.b covers exactly the
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same cases. andi.b should use fractionally less power than bclri.b in
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most hardware implementations so it is used in preference to bclri.b.
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vshf.w:
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It is not possible to emit vshf.w when the shuffle description is
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constant since shf.w covers exactly the same cases. shf.w is used
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instead. It is also impossible for the shuffle description to be
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unknown at compile-time due to the definition of shufflevector in
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LLVM IR.
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vshf.[bhwd]
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When the shuffle description describes a splat operation, splat.[bhwd]
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instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
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and pck* instructions, this is matched from MipsISD::VSHF instead of
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a special-case MipsISD node.
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ilvl.d, pckev.d:
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It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
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same shuffle. ilvev.d will be emitted instead.
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ilvr.d, ilvod.d, pckod.d:
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It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
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same shuffle. ilvod.d will be emitted instead.
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splat.[bhwd]
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The intrinsic will work as expected. However, unlike other intrinsics
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it lowers directly to MipsISD::VSHF instead of using common IR.
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splati.w:
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It is not possible to emit splati.w since shf.w covers the same cases.
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shf.w will be emitted instead.
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copy_s.w:
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On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
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copy_u.w. This is semantically equivalent since the general-purpose
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register file is 32-bits wide.
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binsri.[bhwd], binsli.[bhwd]:
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These two operations are equivalent to each other with the operands
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swapped and condition inverted. The compiler may use either one as
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appropriate.
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Furthermore, the compiler may use bsel.[bhwd] for some masks that do
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not survive the legalization process (this is a bug and will be fixed).
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bmnz.v, bmz.v, bsel.v:
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These three operations differ only in the operand that is tied to the
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result and the order of the operands.
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It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is
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the same operation and will be emitted instead.
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In future, the compiler may choose between these three instructions
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according to register allocation.
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These three operations can be very confusing so here is a mapping
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between the instructions and the vselect node in one place:
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bmz.v wd, ws, wt/i8 -> (vselect wt/i8, wd, ws)
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bmnz.v wd, ws, wt/i8 -> (vselect wt/i8, ws, wd)
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bsel.v wd, ws, wt/i8 -> (vselect wd, wt/i8, ws)
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bmnzi.b, bmzi.b:
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Like their non-immediate counterparts, bmnzi.v and bmzi.v are the same
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operation with the operands swapped. bmnzi.v will (currently) be emitted
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for both cases.
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bseli.v:
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Unlike the non-immediate versions, bseli.v is distinguishable from
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bmnzi.b and bmzi.b and can be emitted.
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