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Summary: Before this patch, `relaxInstruction` takes three arguments, the first argument refers to the instruction before relaxation and the third argument is the output instruction after relaxation. There are two quite strange things: 1) The first argument's type is `const MCInst &`, the third argument's type is `MCInst &`, but they may be aliased to the same variable 2) The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third argument is a fresh uninitialized `MCInst` even if `relaxInstruction` may be called like `relaxInstruction(Relaxed, STI, Relaxed)` in a loop. In this patch, we drop the thrid argument, and let `relaxInstruction` directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, and breaks the assumption of ARM, AMDGPU, RISC-V, Hexagon. Reviewers: Razer6, MaskRay, jyknight, asb, luismarques, enderby, rtaylor, colinl, bcain Reviewed By: Razer6, MaskRay, bcain Subscribers: bcain, nickdesaulniers, nathanchance, wuzish, annita.zhang, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, tpr, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78364 |
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| .. | ||
| AsmParser | ||
| Disassembler | ||
| MCTargetDesc | ||
| TargetInfo | ||
| Utils | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| RISCV.h | ||
| RISCV.td | ||
| RISCVAsmPrinter.cpp | ||
| RISCVCallingConv.td | ||
| RISCVCallLowering.cpp | ||
| RISCVCallLowering.h | ||
| RISCVExpandPseudoInsts.cpp | ||
| RISCVFrameLowering.cpp | ||
| RISCVFrameLowering.h | ||
| RISCVInstrFormats.td | ||
| RISCVInstrFormatsC.td | ||
| RISCVInstrInfo.cpp | ||
| RISCVInstrInfo.h | ||
| RISCVInstrInfo.td | ||
| RISCVInstrInfoA.td | ||
| RISCVInstrInfoB.td | ||
| RISCVInstrInfoC.td | ||
| RISCVInstrInfoD.td | ||
| RISCVInstrInfoF.td | ||
| RISCVInstrInfoM.td | ||
| RISCVInstructionSelector.cpp | ||
| RISCVISelDAGToDAG.cpp | ||
| RISCVISelDAGToDAG.h | ||
| RISCVISelLowering.cpp | ||
| RISCVISelLowering.h | ||
| RISCVLegalizerInfo.cpp | ||
| RISCVLegalizerInfo.h | ||
| RISCVMachineFunctionInfo.h | ||
| RISCVMCInstLower.cpp | ||
| RISCVMergeBaseOffset.cpp | ||
| RISCVRegisterBankInfo.cpp | ||
| RISCVRegisterBankInfo.h | ||
| RISCVRegisterBanks.td | ||
| RISCVRegisterInfo.cpp | ||
| RISCVRegisterInfo.h | ||
| RISCVRegisterInfo.td | ||
| RISCVSchedRocket32.td | ||
| RISCVSchedRocket64.td | ||
| RISCVSchedule.td | ||
| RISCVSubtarget.cpp | ||
| RISCVSubtarget.h | ||
| RISCVSystemOperands.td | ||
| RISCVTargetMachine.cpp | ||
| RISCVTargetMachine.h | ||
| RISCVTargetObjectFile.cpp | ||
| RISCVTargetObjectFile.h | ||
| RISCVTargetTransformInfo.cpp | ||
| RISCVTargetTransformInfo.h | ||