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0cfbe42fbc
Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper, RKSimon Subscribers: RKSimon, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19795 llvm-svn: 269911
831 lines
32 KiB
TableGen
831 lines
32 KiB
TableGen
//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, referred
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// to here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget state
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//
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def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
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"64-bit mode (x86_64)">;
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def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
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"32-bit mode (80386)">;
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def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
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"16-bit mode (i8086)">;
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features
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//===----------------------------------------------------------------------===//
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def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
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"Enable X87 float instructions">;
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
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"Support POPCNT instruction">;
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def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
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"Support fxsave/fxrestore instructions">;
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def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
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"Support xsave instructions">;
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def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
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"Support xsaveopt instructions">;
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def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
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"Support xsavec instructions">;
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def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
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"Support xsaves instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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// SSE codegen depends on cmovs, and all
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// SSE1+ processors support them.
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[FeatureCMOV]>;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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// The MMX subtarget feature is separate from the rest of the SSE features
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// because it's important (for odd compatibility reasons) to be able to
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// turn it off explicitly while allowing SSE+ to be on.
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def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
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"Enable MMX instructions">;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
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"64-bit with cmpxchg16b",
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[Feature64Bit]>;
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def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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"Bit testing of memory is slow">;
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def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
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"SHLD instruction is slow">;
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// FIXME: This should not apply to CPUs that do not have SSE.
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def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
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"IsUAMem16Slow", "true",
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"Slow unaligned 16-byte memory access">;
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def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
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"IsUAMem32Slow", "true",
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"Slow unaligned 32-byte memory access">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions",
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[FeatureSSE3]>;
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def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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"Enable AVX instructions",
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[FeatureSSE42]>;
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
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"Enable AVX-512 instructions",
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[FeatureAVX2]>;
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def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions",
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[FeatureAVX512]>;
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def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions",
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[FeatureAVX512]>;
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def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions",
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[FeatureAVX512]>;
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def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1",
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"true",
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"Prefetch with Intent to Write and T1 Hint">;
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def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
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"Enable AVX-512 Doubleword and Quadword Instructions",
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[FeatureAVX512]>;
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def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
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"Enable AVX-512 Byte and Word Instructions",
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[FeatureAVX512]>;
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def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
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"Enable AVX-512 Vector Length eXtensions",
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[FeatureAVX512]>;
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def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
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"Enable AVX-512 Vector Bit Manipulation Instructions",
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[FeatureAVX512]>;
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def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
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"Enable AVX-512 Integer Fused Multiple-Add",
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[FeatureAVX512]>;
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def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
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"Enable protection keys">;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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[FeatureSSE2]>;
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def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
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"Enable three-operand fused multiple-add",
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[FeatureAVX]>;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add",
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[FeatureAVX, FeatureSSE4A]>;
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def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
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"Enable XOP instructions",
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[FeatureFMA4]>;
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def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
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"HasSSEUnalignedMem", "true",
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"Allow unaligned memory operands with SSE instructions">;
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def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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"Enable AES instructions",
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[FeatureSSE2]>;
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def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
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"Enable TBM instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions",
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[FeatureAVX]>;
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def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
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"Support FS/GS Base instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
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"Support BMI2 instructions">;
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def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
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"Support RTM instructions">;
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def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
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"Support HLE">;
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def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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"Support ADX instructions">;
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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"Support RDSEED instruction">;
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def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
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"Support LAHF and SAHF instructions">;
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def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
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"Enable MONITORX/MWAITX timer functionality">;
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def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
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"Support MPX instructions">;
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def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
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"Use LEA for adjusting the stack pointer">;
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def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
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"HasSlowDivide32", "true",
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"Use 8-bit divide for positive values less than 256">;
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def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
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"HasSlowDivide64", "true",
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"Use 16-bit divide for positive values less than 65536">;
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def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
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"PadShortFunctions", "true",
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"Pad short functions">;
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def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true",
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"Invalidate Process-Context Identifier">;
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def FeatureVMFUNC : SubtargetFeature<"vmfunc", "HasVMFUNC", "true",
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"VM Functions">;
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def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
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"Supervisor Mode Access Protection">;
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def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
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"Enable Software Guard Extensions">;
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def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
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"Flush A Cache Line Optimized">;
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def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
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"Enable Persistent Commit">;
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def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
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"Cache Line Write Back">;
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// TODO: This feature ought to be renamed.
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// What it really refers to are CPUs for which certain instructions
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// (which ones besides the example below?) are microcoded.
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// The best examples of this are the memory forms of CALL and PUSH
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// instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
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def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
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"CallRegIndirect", "true",
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"Call register indirect">;
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def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
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"LEA instruction needs inputs at AG stage">;
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def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
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"LEA instruction with certain arguments is slow">;
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def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
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"INC and DEC instructions are slower than ADD and SUB">;
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def FeatureSoftFloat
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: SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software floating point features.">;
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// On at least some AMD processors, there is no performance hazard to writing
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// only the lower parts of a YMM register without clearing the upper part.
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def FeatureFastPartialYMMWrite
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: SubtargetFeature<"fast-partial-ymm-write", "HasFastPartialYMMWrite",
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"true", "Partial writes to YMM registers are fast">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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include "X86Schedule.td"
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def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
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"Intel Atom processors">;
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def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
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"Intel Silvermont processors">;
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class Proc<string Name, list<SubtargetFeature> Features>
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: ProcessorModel<Name, GenericModel, Features>;
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def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
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def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureCMOV, FeatureFXSR]>;
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def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE1, FeatureFXSR]>;
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def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>;
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// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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// The intent is to enable it for pentium4 which is the current default
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// processor in a vanilla 32-bit clang compilation when no specific
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// architecture is specified. This generally gives a nice performance
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// increase on silvermont, with largely neutral behavior on other
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// contemporary large core processors.
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// pentium-m, pentium4m, prescott and nocona are included as a preventative
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// measure to avoid performance surprises, in case clang's default cpu
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// changes slightly.
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def : ProcessorModel<"pentium-m", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
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def : ProcessorModel<"pentium4", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR]>;
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def : ProcessorModel<"pentium4m", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>;
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// Intel Quark.
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def : Proc<"lakemont", []>;
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
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FeatureFXSR, FeatureSlowBTMem]>;
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// NetBurst.
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def : ProcessorModel<"prescott", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
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FeatureFXSR, FeatureSlowBTMem]>;
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def : ProcessorModel<"nocona", GenericPostRAModel, [
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FeatureX87,
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FeatureSlowUAMem16,
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FeatureMMX,
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FeatureSSE3,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem
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]>;
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// Intel Core 2 Solo/Duo.
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def : ProcessorModel<"core2", SandyBridgeModel, [
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FeatureX87,
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FeatureSlowUAMem16,
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FeatureMMX,
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FeatureSSSE3,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureLAHFSAHF
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]>;
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def : ProcessorModel<"penryn", SandyBridgeModel, [
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FeatureX87,
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FeatureSlowUAMem16,
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FeatureMMX,
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FeatureSSE41,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureLAHFSAHF
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]>;
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// Atom CPUs.
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class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
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ProcIntelAtom,
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FeatureX87,
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FeatureSlowUAMem16,
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FeatureMMX,
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FeatureSSSE3,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeatureSlowBTMem,
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FeatureLEAForSP,
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FeatureSlowDivide32,
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FeatureSlowDivide64,
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FeatureCallRegIndirect,
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FeatureLEAUsesAG,
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FeaturePadShortFunctions,
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FeatureLAHFSAHF
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]>;
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def : BonnellProc<"bonnell">;
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def : BonnellProc<"atom">; // Pin the generic name to the baseline.
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class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
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ProcIntelSLM,
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FeatureX87,
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FeatureMMX,
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FeatureSSE42,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeaturePOPCNT,
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FeaturePCLMUL,
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FeatureAES,
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FeatureSlowDivide64,
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FeatureCallRegIndirect,
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FeaturePRFCHW,
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FeatureSlowLEA,
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FeatureSlowIncDec,
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FeatureSlowBTMem,
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FeatureLAHFSAHF
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]>;
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def : SilvermontProc<"silvermont">;
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def : SilvermontProc<"slm">; // Legacy alias.
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// "Arrandale" along with corei3 and corei5
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class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureX87,
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FeatureMMX,
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FeatureSSE42,
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FeatureFXSR,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeaturePOPCNT,
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FeatureLAHFSAHF
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]>;
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def : NehalemProc<"nehalem">;
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def : NehalemProc<"corei7">;
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
|
|
class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSE42,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeatureSlowBTMem,
|
|
FeaturePOPCNT,
|
|
FeatureAES,
|
|
FeaturePCLMUL,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
def : WestmereProc<"westmere">;
|
|
|
|
class ProcessorFeatures<list<SubtargetFeature> Inherited,
|
|
list<SubtargetFeature> NewFeatures> {
|
|
list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
|
|
}
|
|
|
|
class ProcModel<string Name, SchedMachineModel Model,
|
|
list<SubtargetFeature> ProcFeatures,
|
|
list<SubtargetFeature> OtherFeatures> :
|
|
ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
|
|
|
|
// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
|
|
// rather than a superset.
|
|
def SNBFeatures : ProcessorFeatures<[], [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePOPCNT,
|
|
FeatureAES,
|
|
FeaturePCLMUL,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
|
|
class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
|
|
SNBFeatures.Value, [
|
|
FeatureSlowBTMem,
|
|
FeatureSlowUAMem32
|
|
]>;
|
|
def : SandyBridgeProc<"sandybridge">;
|
|
def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
|
|
|
|
def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
|
|
FeatureRDRAND,
|
|
FeatureF16C,
|
|
FeatureFSGSBase
|
|
]>;
|
|
|
|
class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
|
|
IVBFeatures.Value, [
|
|
FeatureSlowBTMem,
|
|
FeatureSlowUAMem32
|
|
]>;
|
|
def : IvyBridgeProc<"ivybridge">;
|
|
def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
|
|
|
|
def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
|
|
FeatureAVX2,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureFMA,
|
|
FeatureLZCNT,
|
|
FeatureMOVBE,
|
|
FeatureINVPCID,
|
|
FeatureVMFUNC,
|
|
FeatureRTM,
|
|
FeatureHLE,
|
|
FeatureSlowIncDec
|
|
]>;
|
|
|
|
class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
|
|
HSWFeatures.Value, []>;
|
|
def : HaswellProc<"haswell">;
|
|
def : HaswellProc<"core-avx2">; // Legacy alias.
|
|
|
|
def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
|
|
FeatureADX,
|
|
FeatureRDSEED,
|
|
FeatureSMAP
|
|
]>;
|
|
class BroadwellProc<string Name> : ProcModel<Name, HaswellModel,
|
|
BDWFeatures.Value, []>;
|
|
def : BroadwellProc<"broadwell">;
|
|
|
|
def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
|
|
FeatureMPX,
|
|
FeatureXSAVEC,
|
|
FeatureXSAVES,
|
|
FeatureSGX,
|
|
FeatureCLFLUSHOPT
|
|
]>;
|
|
|
|
// FIXME: define SKL model
|
|
class SkylakeClientProc<string Name> : ProcModel<Name, HaswellModel,
|
|
SKLFeatures.Value, []>;
|
|
def : SkylakeClientProc<"skylake">;
|
|
|
|
// FIXME: define KNL model
|
|
class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
|
|
IVBFeatures.Value, [
|
|
FeatureAVX512,
|
|
FeatureERI,
|
|
FeatureCDI,
|
|
FeaturePFI,
|
|
FeaturePREFETCHWT1,
|
|
FeatureADX,
|
|
FeatureRDSEED,
|
|
FeatureMOVBE,
|
|
FeatureLZCNT,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureFMA
|
|
]>;
|
|
def : KnightsLandingProc<"knl">;
|
|
|
|
def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
|
|
FeatureAVX512,
|
|
FeatureCDI,
|
|
FeatureDQI,
|
|
FeatureBWI,
|
|
FeatureVLX,
|
|
FeaturePKU,
|
|
FeaturePCOMMIT,
|
|
FeatureCLWB
|
|
]>;
|
|
|
|
// FIXME: define SKX model
|
|
class SkylakeServerProc<string Name> : ProcModel<Name, HaswellModel,
|
|
SKXFeatures.Value, []>;
|
|
def : SkylakeServerProc<"skylake-avx512">;
|
|
def : SkylakeServerProc<"skx">; // Legacy alias.
|
|
|
|
def CNLFeatures : ProcessorFeatures<SKXFeatures.Value, [
|
|
FeatureVBMI,
|
|
FeatureIFMA,
|
|
FeatureSHA
|
|
]>;
|
|
|
|
class CannonlakeProc<string Name> : ProcModel<Name, HaswellModel,
|
|
CNLFeatures.Value, []>;
|
|
def : CannonlakeProc<"cannonlake">;
|
|
|
|
// AMD CPUs.
|
|
|
|
def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
|
|
def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
|
|
Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
|
|
Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
|
|
Feature3DNowA, FeatureFXSR, FeatureSlowBTMem,
|
|
FeatureSlowSHLD]>;
|
|
def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2,
|
|
Feature3DNowA, FeatureFXSR, Feature64Bit,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3,
|
|
Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B,
|
|
FeatureSlowBTMem, FeatureSlowSHLD]>;
|
|
def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA,
|
|
FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
|
|
FeatureLAHFSAHF]>;
|
|
def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA,
|
|
FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT,
|
|
FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD,
|
|
FeatureLAHFSAHF]>;
|
|
|
|
// Bobcat
|
|
def : Proc<"btver1", [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureSSSE3,
|
|
FeatureSSE4A,
|
|
FeatureFXSR,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePRFCHW,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
|
|
// Jaguar
|
|
def : ProcessorModel<"btver2", BtVer2Model, [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureCMPXCHG16B,
|
|
FeaturePRFCHW,
|
|
FeatureAES,
|
|
FeaturePCLMUL,
|
|
FeatureBMI,
|
|
FeatureF16C,
|
|
FeatureMOVBE,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureXSAVEOPT,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF,
|
|
FeatureFastPartialYMMWrite
|
|
]>;
|
|
|
|
// Bulldozer
|
|
def : Proc<"bdver1", [
|
|
FeatureX87,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
// Piledriver
|
|
def : Proc<"bdver2", [
|
|
FeatureX87,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureF16C,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureBMI,
|
|
FeatureTBM,
|
|
FeatureFMA,
|
|
FeatureSlowSHLD,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
|
|
// Steamroller
|
|
def : Proc<"bdver3", [
|
|
FeatureX87,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureMMX,
|
|
FeatureAVX,
|
|
FeatureFXSR,
|
|
FeatureSSE4A,
|
|
FeatureF16C,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureBMI,
|
|
FeatureTBM,
|
|
FeatureFMA,
|
|
FeatureXSAVEOPT,
|
|
FeatureSlowSHLD,
|
|
FeatureFSGSBase,
|
|
FeatureLAHFSAHF
|
|
]>;
|
|
|
|
// Excavator
|
|
def : Proc<"bdver4", [
|
|
FeatureX87,
|
|
FeatureMMX,
|
|
FeatureAVX2,
|
|
FeatureFXSR,
|
|
FeatureXOP,
|
|
FeatureFMA4,
|
|
FeatureCMPXCHG16B,
|
|
FeatureAES,
|
|
FeaturePRFCHW,
|
|
FeaturePCLMUL,
|
|
FeatureF16C,
|
|
FeatureLZCNT,
|
|
FeaturePOPCNT,
|
|
FeatureXSAVE,
|
|
FeatureBMI,
|
|
FeatureBMI2,
|
|
FeatureTBM,
|
|
FeatureFMA,
|
|
FeatureXSAVEOPT,
|
|
FeatureFSGSBase,
|
|
FeatureLAHFSAHF,
|
|
FeatureMWAITX
|
|
]>;
|
|
|
|
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
|
|
|
|
def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
|
|
def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
|
|
def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
|
|
FeatureSSE1, FeatureFXSR]>;
|
|
|
|
// We also provide a generic 64-bit specific x86 processor model which tries to
|
|
// be good for modern chips without enabling instruction set encodings past the
|
|
// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
|
|
// modern 64-bit x86 chip, and enables features that are generally beneficial.
|
|
//
|
|
// We currently use the Sandy Bridge model as the default scheduling model as
|
|
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
|
|
// covers a huge swath of x86 processors. If there are specific scheduling
|
|
// knobs which need to be tuned differently for AMD chips, we might consider
|
|
// forming a common base for them.
|
|
def : ProcessorModel<"x86-64", SandyBridgeModel,
|
|
[FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR,
|
|
Feature64Bit, FeatureSlowBTMem ]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86RegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86InstrInfo.td"
|
|
|
|
def X86InstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Calling Conventions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "X86CallingConv.td"
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Parser
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def ATTAsmParserVariant : AsmParserVariant {
|
|
int Variant = 0;
|
|
|
|
// Variant name.
|
|
string Name = "att";
|
|
|
|
// Discard comments in assembly strings.
|
|
string CommentDelimiter = "#";
|
|
|
|
// Recognize hard coded registers.
|
|
string RegisterPrefix = "%";
|
|
}
|
|
|
|
def IntelAsmParserVariant : AsmParserVariant {
|
|
int Variant = 1;
|
|
|
|
// Variant name.
|
|
string Name = "intel";
|
|
|
|
// Discard comments in assembly strings.
|
|
string CommentDelimiter = ";";
|
|
|
|
// Recognize hard coded registers.
|
|
string RegisterPrefix = "";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Assembly Printers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// The X86 target supports two different syntaxes for emitting machine code.
|
|
// This is controlled by the -x86-asm-syntax={att|intel}
|
|
def ATTAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "ATTInstPrinter";
|
|
int Variant = 0;
|
|
}
|
|
def IntelAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "IntelInstPrinter";
|
|
int Variant = 1;
|
|
}
|
|
|
|
def X86 : Target {
|
|
// Information about the instructions...
|
|
let InstructionSet = X86InstrInfo;
|
|
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
|
|
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
|
|
}
|