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216a9fc9a1
Summary: The symbols use the processor-specific SHN_AMDGPU_LDS section index introduced with a previous change. The linker is then expected to resolve relocations, which are also emitted. Initially disabled for HSA and PAL environments until they have caught up in terms of linker and runtime loader. Some notes: - The llvm.amdgcn.groupstaticsize intrinsics can no longer be lowered to a constant at compile times, which means some tests can no longer be applied. The current "solution" is a terrible hack, but the intrinsic isn't used by Mesa, so we can keep it for now. - We no longer know the full LDS size per kernel at compile time, which means that we can no longer generate a relevant error message at compile time. It would be possible to add a check for the size of individual variables, but ultimately the linker will have to perform the final check. Change-Id: If66dbf33fccfbf3609aefefa2558ac0850d42275 Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin Subscribers: qcolombet, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61494 llvm-svn: 364297
140 lines
5.3 KiB
LLVM
140 lines
5.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
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; the global address space(1) uses 64-bit pointers. These tests check to make sure
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; the correct pointer size is used for the local address space.
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; The e{{32|64}} suffix on the instructions refers to the encoding size and not
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; the size of the operands. The operand size is denoted in the instruction name.
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; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
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; instructions with B64, U64, and I64 take 64-bit operands.
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; FUNC-LABEL: {{^}}local_address_load:
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; SI: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]]
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; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
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define amdgpu_kernel void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = load i32, i32 addrspace(3)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep:
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; SI: s_add_i32 [[SPTR:s[0-9]]]
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; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; SI: ds_read_b32 [[VPTR]]
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define amdgpu_kernel void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
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entry:
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%0 = getelementptr i32, i32 addrspace(3)* %in, i32 %offset
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%1 = load i32, i32 addrspace(3)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep_const_offset:
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; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
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define amdgpu_kernel void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = getelementptr i32, i32 addrspace(3)* %in, i32 1
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%1 = load i32, i32 addrspace(3)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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; FUNC-LABEL: {{^}}local_address_gep_large_const_offset:
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; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; SI: ds_read_b32 [[VPTR]]
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define amdgpu_kernel void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = getelementptr i32, i32 addrspace(3)* %in, i32 16385
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%1 = load i32, i32 addrspace(3)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}null_32bit_lds_ptr:
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; SI: v_cmp_ne_u32
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; SI-NOT: v_cmp_ne_u32
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; SI: v_cndmask_b32
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define amdgpu_kernel void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind {
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%cmp = icmp ne i32 addrspace(3)* %lds, null
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%x = select i1 %cmp, i32 123, i32 456
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}mul_32bit_ptr:
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; SI: s_mul_i32
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; SI-NEXT: s_add_i32
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; SI: ds_read_b32
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define amdgpu_kernel void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) {
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%ptr = getelementptr [3 x float], [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
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%val = load float, float addrspace(3)* %ptr
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store float %val, float addrspace(1)* %out
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ret void
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}
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@g_lds = addrspace(3) global float undef, align 4
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; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
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; SI: v_mov_b32_e32 [[PTR:v[0-9]+]], g_lds@abs32@lo
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; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
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define amdgpu_kernel void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
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%val = load float, float addrspace(3)* @g_lds
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store float %val, float addrspace(1)* %out
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ret void
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}
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@ptr = addrspace(3) global i32 addrspace(3)* undef
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@dst = addrspace(3) global [16383 x i32] undef
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; FUNC-LABEL: {{^}}global_ptr:
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; SI: ds_write_b32
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define amdgpu_kernel void @global_ptr() nounwind {
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store i32 addrspace(3)* getelementptr ([16383 x i32], [16383 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_store:
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; SI: ds_write_b32
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define amdgpu_kernel void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
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store i32 %val, i32 addrspace(3)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep_store:
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; SI: s_add_i32 [[SADDR:s[0-9]+]],
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; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
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; SI: ds_write_b32 [[ADDR]], v{{[0-9]+}}
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define amdgpu_kernel void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) {
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%gep = getelementptr i32, i32 addrspace(3)* %out, i32 %offset
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store i32 %val, i32 addrspace(3)* %gep, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep_const_offset_store:
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; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
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define amdgpu_kernel void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
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%gep = getelementptr i32, i32 addrspace(3)* %out, i32 1
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store i32 %val, i32 addrspace(3)* %gep, align 4
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ret void
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store:
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; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
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define amdgpu_kernel void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
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%gep = getelementptr i32, i32 addrspace(3)* %out, i32 16385
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store i32 %val, i32 addrspace(3)* %gep, align 4
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ret void
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}
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