mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
0e8face627
Now we have vec3 MVTs, this commit implements dwordx3 variants of the buffer intrinsics. On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4 instruction, and a dwordx3 buffer store intrinsic is not supported. We need to support the dwordx3 load intrinsic because it is generated by subtarget-unaware code in InstCombine. Differential Revision: https://reviews.llvm.org/D58904 Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e llvm-svn: 356755
61 lines
2.8 KiB
LLVM
61 lines
2.8 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=gfx600 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,SI
|
|
;RUN: llc < %s -march=amdgcn -mcpu=gfx700 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,GCNX3
|
|
|
|
;CHECK-LABEL: {{^}}buffer_load_format_immoffs_x3:
|
|
;SI: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:42
|
|
;GCNX3: buffer_load_format_xyz v[0:2], off, s[0:3], 0 offset:42
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps <3 x float> @buffer_load_format_immoffs_x3(<4 x i32> inreg) {
|
|
main_body:
|
|
%data = call <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
|
|
ret <3 x float> %data
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}buffer_load_immoffs_x3:
|
|
;SI: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
|
|
;GCNX3: buffer_load_dwordx3 v[0:2], off, s[0:3], 0 offset:40
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps <3 x float> @buffer_load_immoffs_x3(<4 x i32> inreg) {
|
|
main_body:
|
|
%data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i1 0, i1 0)
|
|
ret <3 x float> %data
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}buffer_raw_load_immoffs_x3:
|
|
;SI: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
|
|
;GCNX3: buffer_load_dwordx3 v[0:2], off, s[0:3], 0 offset:40
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps <3 x float> @buffer_raw_load_immoffs_x3(<4 x i32> inreg) {
|
|
main_body:
|
|
%data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %0, i32 40, i32 0, i32 0)
|
|
ret <3 x float> %data
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}buffer_struct_load_format_immoffs_x3:
|
|
;SI: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
|
|
;GCNX3: buffer_load_format_xyz v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps <3 x float> @buffer_struct_load_format_immoffs_x3(<4 x i32> inreg) {
|
|
main_body:
|
|
%data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
|
|
ret <3 x float> %data
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}struct_buffer_load_immoffs_x3:
|
|
;SI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
|
|
;GCNX3: buffer_load_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps <3 x float> @struct_buffer_load_immoffs_x3(<4 x i32> inreg) {
|
|
main_body:
|
|
%data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0)
|
|
ret <3 x float> %data
|
|
}
|
|
|
|
declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #0
|
|
declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #0
|
|
declare <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32) #0
|
|
declare <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32>, i32, i32, i32) #0
|
|
declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32) #0
|
|
declare <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32>, i32, i32, i32, i32) #0
|
|
|