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22ba99e3f8
"Divergence driven ISel. Assign register class for cross block values
according to the divergence."
that discovered the design flaw leading to several issues that
required to be solved before.
This change reverts AMDGPU specific changes and keeps common part
unaffected.
llvm-svn: 362749
75 lines
1.6 KiB
YAML
75 lines
1.6 KiB
YAML
# RUN: llc -march=amdgcn -run-pass si-fix-sgpr-copies %s -o - | FileCheck %s -check-prefixes=GCN
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---
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name: phi_visit_order
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_32_xm0 }
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- { id: 1, class: sreg_64 }
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- { id: 2, class: sreg_32_xm0 }
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- { id: 7, class: vgpr_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: vgpr_32 }
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- { id: 10, class: sreg_64 }
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- { id: 11, class: sreg_32_xm0 }
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body: |
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; GCN-LABEL: name: phi_visit_order
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; GCN: V_ADD_I32
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bb.0:
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liveins: $vgpr0
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%7 = COPY $vgpr0
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%8 = S_MOV_B32 0
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bb.1:
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%0 = PHI %8, %bb.0, %0, %bb.1, %2, %bb.2
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%9 = V_MOV_B32_e32 9, implicit $exec
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%10 = V_CMP_EQ_U32_e64 %7, %9, implicit $exec
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%1 = SI_IF %10, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
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S_BRANCH %bb.1
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bb.2:
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SI_END_CF %1, implicit-def $exec, implicit-def $scc, implicit $exec
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%11 = S_MOV_B32 1
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%2 = S_ADD_I32 %0, %11, implicit-def $scc
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S_BRANCH %bb.1
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...
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---
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# GCN-LABEL: name: dead_illegal_virtreg_copy
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# GCN: %0:vgpr_32 = COPY $vgpr0
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# GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
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# GCN: S_ENDPGM 0, implicit %0
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name: dead_illegal_virtreg_copy
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_32_xm0 = COPY %0
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S_ENDPGM 0, implicit %1
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...
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---
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# GCN-LABEL: name: dead_illegal_physreg_copy
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# GCN %2:vgpr_32 = COPY $vgpr0
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# GCN: %1:sreg_32_xm0 = IMPLICIT_DEF
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# GCN: S_ENDPGM 0, implicit %2
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name: dead_illegal_physreg_copy
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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%0:sreg_32_xm0 = COPY $vgpr0
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%1:sreg_32_xm0 = COPY %0
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S_ENDPGM 0, implicit %1
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...
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