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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/TableGen
Jakob Stoklund Olesen a28aa26057 Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

llvm-svn: 108095
2010-07-11 17:01:17 +00:00
..
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AnonDefinitionOnDemand.td
BitsInitOverflow.td
cast.td
CStyleComment.td
DagDefSubst.td
DagIntSubst.td
defmclass.td Fix a subtle multiclass bug: when using class inheritance on 2010-06-22 20:30:50 +00:00
DefmInherit.td
DefmInsideMultiClass.td
dg.exp
eq.td
eqbit.td let the '!eq' expression support 'int' and 'bit' types 2010-06-16 23:24:12 +00:00
foreach.td
ForwardRef.td
GeneralList.td
if.td
ifbit.td For a tablegen expression such as !if(a,b,c), let 'a' 2010-06-17 00:31:36 +00:00
Include.inc
Include.td
IntBitInit.td
LazyChange.td
LetInsideMultiClasses.td
lisp.td
ListArgs.td
ListArgsSimple.td
ListConversion.td
ListSlices.td
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
nameconcat.td
nested-comment.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td Remove TargetInstrInfo::copyRegToReg entirely. 2010-07-11 17:01:17 +00:00
TargetInstrSpec.td
TemplateArgRename.td
Tree.td
TreeNames.td
UnsetBitInit.td
UnterminatedComment.td
usevalname.td Fix a tblgen bug. 2010-06-23 19:50:39 +00:00