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38 lines
923 B
TableGen
38 lines
923 B
TableGen
// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def REG : Register<"REG">;
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def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
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class SysReg<bits<12> op> {
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bits<12> Encoding = op;
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}
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def SR : SysReg<0b111100001111>;
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class Pseudo<dag outs, dag ins, list<dag> pattern>
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: Instruction {
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let Pattern = pattern;
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let isPseudo = 1;
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}
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def INSTR : Instruction {
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let OutOperandList = (outs GPR:$rd);
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let InOperandList = (ins i32imm:$val);
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let Pattern = [];
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}
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def PSEUDO : Pseudo<(outs GPR:$rd), (ins),
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[(set GPR:$rd, (i32 SR.Encoding))]>,
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PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
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// CHECK: .addOperand(MCOperand::createImm(3855));
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