Tim Northover 4f03f012c7 GlobalISel: forbid physical registers on generic MIs. ... We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132		2016-08-30 18:52:46 +00:00
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AArch64	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
AMDGPU	MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it	2016-08-24 22:17:45 +00:00
ARM	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Generic	MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it	2016-08-24 22:34:06 +00:00
Hexagon	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Lanai	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Mips	MIRParser: Use shorter cfi identifiers	2016-07-26 18:20:00 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	GlobalISel: forbid physical registers on generic MIs.	2016-08-30 18:52:46 +00:00