mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
4b7f9fd6c6
The VE backend represents vector instructions with an explicit 'i32' vector length operand. In the VE ISA, the vector length is always read from the VL hardware register. The LVLGen pass inserts 'lvl' instructions as necessary to set VL to the right value before each vector instruction. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91416
49 lines
1.1 KiB
CMake
49 lines
1.1 KiB
CMake
add_llvm_component_group(VE)
|
|
|
|
set(LLVM_TARGET_DEFINITIONS VE.td)
|
|
|
|
tablegen(LLVM VEGenRegisterInfo.inc -gen-register-info)
|
|
tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info)
|
|
tablegen(LLVM VEGenDisassemblerTables.inc -gen-disassembler)
|
|
tablegen(LLVM VEGenMCCodeEmitter.inc -gen-emitter)
|
|
tablegen(LLVM VEGenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(LLVM VEGenAsmMatcher.inc -gen-asm-matcher)
|
|
tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel)
|
|
tablegen(LLVM VEGenSubtargetInfo.inc -gen-subtarget)
|
|
tablegen(LLVM VEGenCallingConv.inc -gen-callingconv)
|
|
add_public_tablegen_target(VECommonTableGen)
|
|
|
|
add_llvm_target(VECodeGen
|
|
LVLGen.cpp
|
|
VEAsmPrinter.cpp
|
|
VEFrameLowering.cpp
|
|
VEISelDAGToDAG.cpp
|
|
VEISelLowering.cpp
|
|
VEInstrInfo.cpp
|
|
VEMachineFunctionInfo.cpp
|
|
VEMCInstLower.cpp
|
|
VERegisterInfo.cpp
|
|
VESubtarget.cpp
|
|
VETargetMachine.cpp
|
|
|
|
LINK_COMPONENTS
|
|
Analysis
|
|
AsmPrinter
|
|
CodeGen
|
|
Core
|
|
MC
|
|
SelectionDAG
|
|
VEDesc
|
|
VEInfo
|
|
Support
|
|
Target
|
|
|
|
ADD_TO_COMPONENT
|
|
VE
|
|
)
|
|
|
|
add_subdirectory(AsmParser)
|
|
add_subdirectory(Disassembler)
|
|
add_subdirectory(TargetInfo)
|
|
add_subdirectory(MCTargetDesc)
|