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2348cd927a
These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
32 lines
1.0 KiB
TableGen
32 lines
1.0 KiB
TableGen
// Common target boilerplate for GlobalISelEmitter tests.
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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class MyTargetGenericInstruction : GenericInstruction {
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let Namespace = "MyTarget";
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}
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def GPR32Op : RegisterOperand<GPR32>;
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def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
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def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
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def FPR32Op : RegisterOperand<FPR32>;
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def B0 : Register<"b0"> { let Namespace = "MyTarget"; }
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def GPR8 : RegisterClass<"MyTarget", [i8], 8, (add B0)>;
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def GPR8Op : RegisterOperand<GPR8>;
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def V0 : Register<"v0"> { let Namespace = "MyTarget"; }
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def VecReg128 : RegisterClass<"MyTarget", [v4i32], 128, (add V0)>;
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def p0 : PtrValueType <i32, 0>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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