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https://github.com/RPCS3/llvm-mirror.git
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099f4c5254
Allow a target to do something other than search for copies that will avoid cross register bank copies. Implement for SI by only rewriting the most basic copies, so it should look through anything like a subregister extract. I'm not entirely satisified with this because it seems like eliminating a reg_sequence that isn't fully used should work generically for all targets without them having to override something. However, it seems to be tricky to have a simple implementation of this without rewriting to invalid kinds of subregister copies on some targets. I'm not sure if there is currently a generic way to easily check if a subregister index would be valid for the current use. The current set of TargetRegisterInfo::get*Class functions don't quite behave like I would expect (e.g. getSubClassWithSubReg returns the maximal register class rather than the minimal), so I'm not sure how to make the generic test keep searching if SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making the default implementation to check for simple copies breaks a variety of ARM and x86 tests by producing illegal subregister uses. The ARM tests are not actually changed since it should still be using the same sharesSameRegisterFile implementation, this just relaxes them to not check for specific registers. llvm-svn: 248478
311 lines
11 KiB
LLVM
311 lines
11 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test2:
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; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = and <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test4:
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = and <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i32:
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; SI: s_and_b32
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define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i32:
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
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define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) {
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%and = and i32 %a, 1234567
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i32:
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; SI: v_and_b32
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define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%b = load i32, i32 addrspace(1)* %bptr, align 4
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_constant_i32
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; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
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define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%and = and i32 %a, 1234567
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32
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; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
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define void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%and = and i32 %a, 64
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32
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; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
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define void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%a = load i32, i32 addrspace(1)* %aptr, align 4
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%and = and i32 %a, -16
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i64
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; SI: s_and_b64
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define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%and = and i64 %a, %b
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Should use SGPRs
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; FUNC-LABEL: {{^}}s_and_i1:
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; SI: v_and_b32
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define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
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%and = and i1 %a, %b
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store i1 %and, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
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%and = and i64 %a, 281474976710655
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64:
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; SI: v_and_b32
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; SI: v_and_b32
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define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%b = load i64, i64 addrspace(1)* %bptr, align 8
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%and = and i64 %a, %b
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64_br:
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; SI: v_and_b32
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; SI: v_and_b32
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define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i32 %cond) {
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entry:
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%b = load i64, i64 addrspace(1)* %bptr, align 8
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%and = and i64 %a, %b
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br label %endif
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endif:
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%tmp1 = phi i64 [%and, %if], [0, %entry]
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store i64 %tmp1, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_constant_i64:
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; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207
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; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], {{v[0-9]+}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], {{v[0-9]+}}
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; SI: buffer_store_dwordx2
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define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 1231231234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Should replace and 0
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; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant:
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; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
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define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 1234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Replace and 0 with mov 0
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; FUNC-LABEL: {{^}}v_and_inline_imm_i64:
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; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
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define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 64
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64
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define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 64
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1
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define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 1
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
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define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 4607182418800017408
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
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define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 13830554455654793216
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
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define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 4602678819172646912
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
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define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 13826050856027422720
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 2.0
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define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 4611686018427387904
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -2.0
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define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 13835058055282163712
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
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define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 4616189618054758400
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
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define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 13839561654909534208
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; Test with the 64-bit integer bitpattern for a 32-bit float in the
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; low 32-bits, which is not a valid 64-bit inline immmediate.
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; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64
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; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
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; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
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define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 1082130432
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Copy of -1 register
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; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64
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; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
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; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
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; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}
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define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, -1065353216
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; Shift into upper 32-bits
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; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_4.0_i64
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; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
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; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
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define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 4647714815446351872
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64
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; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0
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; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
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; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
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define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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%and = and i64 %a, 13871086852301127680
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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