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30264d4391
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
294 lines
7.9 KiB
LLVM
294 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort=1 -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
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; SSE-LABEL: select_fcmp_one_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: ucomiss %xmm1, %xmm0
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; SSE-NEXT: jne LBB0_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: LBB0_2:
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_one_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: vcmpneq_oqss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
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; AVX-NEXT: retq
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%1 = fcmp one float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_one_f64(double %a, double %b, double %c, double %d) {
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; SSE-LABEL: select_fcmp_one_f64:
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; SSE: ## %bb.0:
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; SSE-NEXT: ucomisd %xmm1, %xmm0
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; SSE-NEXT: jne LBB1_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm3, %xmm2
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; SSE-NEXT: LBB1_2:
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_fcmp_one_f64:
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; AVX: ## %bb.0:
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; AVX-NEXT: vcmpneq_oqsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
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; AVX-NEXT: retq
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%1 = fcmp one double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_icmp_eq_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_eq_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: je LBB2_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB2_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_eq_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: je LBB2_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB2_2:
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; AVX-NEXT: retq
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%1 = icmp eq i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ne_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_ne_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jne LBB3_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB3_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_ne_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jne LBB3_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB3_2:
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; AVX-NEXT: retq
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%1 = icmp ne i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ugt_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_ugt_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: ja LBB4_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB4_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_ugt_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: ja LBB4_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB4_2:
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; AVX-NEXT: retq
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%1 = icmp ugt i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_uge_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_uge_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jae LBB5_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB5_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_uge_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jae LBB5_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB5_2:
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; AVX-NEXT: retq
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%1 = icmp uge i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ult_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_ult_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jb LBB6_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB6_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_ult_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jb LBB6_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB6_2:
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; AVX-NEXT: retq
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%1 = icmp ult i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ule_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_ule_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jbe LBB7_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB7_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_ule_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jbe LBB7_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB7_2:
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; AVX-NEXT: retq
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%1 = icmp ule i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_sgt_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_sgt_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jg LBB8_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB8_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_sgt_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jg LBB8_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB8_2:
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; AVX-NEXT: retq
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%1 = icmp sgt i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_sge_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_sge_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jge LBB9_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB9_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_sge_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jge LBB9_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB9_2:
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; AVX-NEXT: retq
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%1 = icmp sge i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_slt_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_slt_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jl LBB10_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB10_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_slt_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jl LBB10_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB10_2:
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; AVX-NEXT: retq
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%1 = icmp slt i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) {
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; SSE-LABEL: select_icmp_sle_f32:
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; SSE: ## %bb.0:
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; SSE-NEXT: cmpq %rsi, %rdi
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; SSE-NEXT: jle LBB11_2
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; SSE-NEXT: ## %bb.1:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: LBB11_2:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: select_icmp_sle_f32:
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; AVX: ## %bb.0:
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; AVX-NEXT: cmpq %rsi, %rdi
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; AVX-NEXT: jle LBB11_2
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; AVX-NEXT: ## %bb.1:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: LBB11_2:
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; AVX-NEXT: retq
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%1 = icmp sle i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define i8 @select_icmp_sle_i8(i64 %a, i64 %b, i8 %c, i8 %d) {
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; CHECK-LABEL: select_icmp_sle_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: cmpq %rsi, %rdi
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; CHECK-NEXT: jle LBB12_2
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; CHECK-NEXT: ## %bb.1:
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: LBB12_2:
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: retq
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%1 = icmp sle i64 %a, %b
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%2 = select i1 %1, i8 %c, i8 %d
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ret i8 %2
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}
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