Craig Topper 97e1f65ff6 [X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix. ...

This encoding is recognized by the CPU, but the behavior is undefined. This makes the disassembler handle it correctly so we don't print bswapl with a 16-bit register.

llvm-svn: 330682

2018-04-24 04:28:02 +00:00

..

AArch64

[AArch64] Fix spelling of ICH_ELRSR_EL2 system register

2018-02-06 09:39:04 +00:00

AMDGPU

[AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32

2018-04-16 12:41:38 +00:00

ARC

[ARC] Add LImm support for J/JL

2018-04-13 15:10:34 +00:00

ARM

[ARM]Decoding MSR with unpredictable destination register causes an assert

2018-03-06 15:21:19 +00:00

Hexagon

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

Lanai

[lanai] Add Lanai backend.

2016-03-28 13:09:54 +00:00

Mips

[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.

2018-04-12 12:37:02 +00:00

PowerPC

[PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.

2018-02-23 15:55:16 +00:00

Sparc

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

2016-03-09 18:20:21 +00:00

SystemZ

[SystemZ] Add support for IBM z14 processor (3/3)

2017-07-17 17:44:20 +00:00

X86

[X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix.

2018-04-24 04:28:02 +00:00

XCore

…