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1ead7346cd
In particular, this makes the code for 64-bit compares on 32-bit targets
much more efficient.
Example:
define i32 @test_slt(i64 %a, i64 %b) {
entry:
%cmp = icmp slt i64 %a, %b
br i1 %cmp, label %bb1, label %bb2
bb1:
ret i32 1
bb2:
ret i32 2
}
Before this patch:
test_slt:
movl 4(%esp), %eax
movl 8(%esp), %ecx
cmpl 12(%esp), %eax
setae %al
cmpl 16(%esp), %ecx
setge %cl
je .LBB2_2
movb %cl, %al
.LBB2_2:
testb %al, %al
jne .LBB2_4
movl $1, %eax
retl
.LBB2_4:
movl $2, %eax
retl
After this patch:
test_slt:
movl 4(%esp), %eax
movl 8(%esp), %ecx
cmpl 12(%esp), %eax
sbbl 16(%esp), %ecx
jge .LBB1_2
movl $1, %eax
retl
.LBB1_2:
movl $2, %eax
retl
Differential Revision: http://reviews.llvm.org/D14496
llvm-svn: 253572
102 lines
2.2 KiB
LLVM
102 lines
2.2 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vucomisd {{.*}}encoding: [0x62
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define double @test1(double %a, double %b) nounwind {
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%tobool = fcmp une double %a, %b
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br i1 %tobool, label %l1, label %l2
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l1:
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%c = fsub double %a, %b
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ret double %c
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l2:
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%c1 = fadd double %a, %b
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ret double %c1
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}
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; CHECK-LABEL: test2
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; CHECK: vucomiss {{.*}}encoding: [0x62
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define float @test2(float %a, float %b) nounwind {
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%tobool = fcmp olt float %a, %b
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br i1 %tobool, label %l1, label %l2
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l1:
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%c = fsub float %a, %b
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ret float %c
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l2:
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%c1 = fadd float %a, %b
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ret float %c1
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}
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; FIXME: Can use vcmpeqss and extract from the mask here in AVX512.
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; CHECK-LABEL: test3
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; CHECK: vucomiss {{.*}}encoding: [0x62
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define i32 @test3(float %a, float %b) {
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%cmp10.i = fcmp oeq float %a, %b
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%conv11.i = zext i1 %cmp10.i to i32
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ret i32 %conv11.i
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}
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; CHECK-LABEL: test5
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; CHECK: ret
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define float @test5(float %p) #0 {
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entry:
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%cmp = fcmp oeq float %p, 0.000000e+00
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%cmp1 = fcmp ogt float %p, 0.000000e+00
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%cond = select i1 %cmp1, float 1.000000e+00, float -1.000000e+00
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br label %return
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return: ; preds = %if.end, %entry
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%retval.0 = phi float [ %cond, %if.end ], [ %p, %entry ]
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ret float %retval.0
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}
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; CHECK-LABEL: test6
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; CHECK: cmpl
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; CHECK-NOT: kmov
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; CHECK: ret
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define i32 @test6(i32 %a, i32 %b) {
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%cmp = icmp eq i32 %a, %b
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%res = zext i1 %cmp to i32
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ret i32 %res
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}
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; CHECK-LABEL: test7
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; CHECK: vucomisd
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; CHECK-NOT: kmov
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; CHECK: ret
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define i32 @test7(double %x, double %y) #2 {
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entry:
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%0 = fcmp one double %x, %y
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%or = zext i1 %0 to i32
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ret i32 %or
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}
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define i32 @test8(i32 %a1, i32 %a2, i32 %a3) {
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%tmp1 = icmp eq i32 %a1, -1
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%tmp2 = icmp eq i32 %a2, -2147483648
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%tmp3 = and i1 %tmp1, %tmp2
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%tmp4 = icmp eq i32 %a3, 0
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%tmp5 = or i1 %tmp3, %tmp4
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%res = select i1 %tmp5, i32 1, i32 %a3
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ret i32 %res
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}
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; CHECK-LABEL: test9
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; CHECK: testb
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; CHECK-NOT: kmov
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; CHECK: ret
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define i32 @test9(i64 %a) {
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%b = and i64 %a, 1
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%cmp10.i = icmp eq i64 %b, 0
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br i1 %cmp10.i, label %A, label %B
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A:
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ret i32 6
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B:
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ret i32 7
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}
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