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250 lines
7.1 KiB
C++
250 lines
7.1 KiB
C++
/* Title: SparcRegClassInfo.h -*- C++ -*-
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Author: Ruchira Sasanka
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Date: Aug 20, 01
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Purpose: Contains the description of integer register class of Sparc
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*/
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#ifndef SPARC_REG_INFO_CLASS_H
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#define SPARC_REG_INFO_CLASS_H
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#include "llvm/Target/MachineRegInfo.h"
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#include "llvm/CodeGen/IGNode.h"
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//-----------------------------------------------------------------------------
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// Integer Register Class
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//-----------------------------------------------------------------------------
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// Int register names in same order as enum in class SparcIntRegOrder
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static const std::string IntRegNames[] = {
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"o0", "o1", "o2", "o3", "o4", "o5", "o7",
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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"i0", "i1", "i2", "i3", "i4", "i5",
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"i6", "i7",
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"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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"o6"
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};
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struct SparcIntRegOrder {
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enum RegsInPrefOrder { // colors possible for a LR (in preferred order)
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// --- following colors are volatile across function calls
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// %g0 can't be used for coloring - always 0
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o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
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// %o6 is sp,
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// all %0's can get modified by a call
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// --- following colors are NON-volatile across function calls
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l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
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i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
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// %i6 is the fp - so not allocated
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// %i7 is the ret address by convention - can be used for others
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// max # of colors reg coloring can allocate (NumOfAvailRegs)
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// --- following colors are not available for allocation within this phase
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// --- but can appear for pre-colored ranges
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i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6
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//*** NOTE: If we decide to use some %g regs, they are volatile
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// (see sparc64ABI)
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// Move the %g regs from the end of the enumeration to just above the
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// enumeration of %o0 (change StartOfAllRegs below)
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// change isRegVloatile method below
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// Also change IntRegNames above.
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};
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// max # of colors reg coloring can allocate
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static unsigned int const NumOfAvailRegs = i6;
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static unsigned int const StartOfNonVolatileRegs = l0;
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static unsigned int const StartOfAllRegs = o0;
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static unsigned int const NumOfAllRegs = o6 + 1;
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static const std::string getRegName(unsigned reg) {
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assert( reg < NumOfAllRegs );
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return IntRegNames[reg];
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}
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};
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struct SparcIntRegClass : public MachineRegClassInfo {
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SparcIntRegClass(unsigned ID)
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: MachineRegClassInfo(ID,
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SparcIntRegOrder::NumOfAvailRegs,
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SparcIntRegOrder::NumOfAllRegs) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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inline bool isRegVolatile(int Reg) const {
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return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
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}
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};
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//-----------------------------------------------------------------------------
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// Float Register Class
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//-----------------------------------------------------------------------------
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static const std::string FloatRegNames[] =
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{
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
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"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
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"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
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"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
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"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
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"f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
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"f60", "f61", "f62", "f63"
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};
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class SparcFloatRegOrder{
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public:
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enum RegsInPrefOrder {
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f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
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f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
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f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
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f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
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f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
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f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
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f60, f61, f62, f63
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};
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// there are 64 regs alltogether but only 32 regs can be allocated at
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// a time.
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static unsigned int const NumOfAvailRegs = 32;
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static unsigned int const NumOfAllRegs = 64;
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static unsigned int const StartOfNonVolatileRegs = f32;
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static unsigned int const StartOfAllRegs = f0;
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static const std::string getRegName(unsigned reg) {
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assert (reg < NumOfAllRegs);
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return FloatRegNames[reg];
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}
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};
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class SparcFloatRegClass : public MachineRegClassInfo {
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int findFloatColor(const LiveRange *LR, unsigned Start,
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unsigned End, std::vector<bool> &IsColorUsedArr) const;
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public:
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SparcFloatRegClass(unsigned ID)
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: MachineRegClassInfo(ID,
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SparcFloatRegOrder::NumOfAvailRegs,
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SparcFloatRegOrder::NumOfAllRegs) {}
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
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// according to Sparc 64 ABI, all %fp regs are volatile
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inline bool isRegVolatile(int Reg) const { return true; }
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};
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//-----------------------------------------------------------------------------
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// Int CC Register Class
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// Only one integer cc register is available. However, this register is
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// referred to as %xcc when instructions like subcc are executed but
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// referred to as %ccr (i.e., %xcc + %icc") when this register is moved
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// into an integer register using RD or WR instrcutions. So, two ids are
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// allocated for two names.
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//-----------------------------------------------------------------------------
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static const std::string IntCCRegNames[] = {
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"xcc", "ccr"
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};
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struct SparcIntCCRegOrder {
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enum RegsInPrefOrder {
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xcc, ccr // only one is available - see the note above
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};
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static const std::string getRegName(unsigned reg) {
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assert(reg < 2);
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return IntCCRegNames[reg];
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}
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};
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struct SparcIntCCRegClass : public MachineRegClassInfo {
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SparcIntCCRegClass(unsigned ID)
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: MachineRegClassInfo(ID, 1, 2) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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if (IsColorUsedArr[0])
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Node->getParentLR()->markForSpill();
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else
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Node->setColor(0); // only one int cc reg is available
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}
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// according to Sparc 64 ABI, %ccr is volatile
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//
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inline bool isRegVolatile(int Reg) const { return true; }
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};
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//-----------------------------------------------------------------------------
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// Float CC Register Class
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// Only 4 Float CC registers are available
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//-----------------------------------------------------------------------------
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static const std::string FloatCCRegNames[] = {
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"fcc0", "fcc1", "fcc2", "fcc3"
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};
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struct SparcFloatCCRegOrder{
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enum RegsInPrefOrder {
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fcc0, fcc1, fcc2, fcc3
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};
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static const std::string getRegName(unsigned reg) {
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assert (reg < 4);
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return FloatCCRegNames[reg];
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}
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};
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struct SparcFloatCCRegClass : public MachineRegClassInfo {
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SparcFloatCCRegClass(unsigned ID)
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: MachineRegClassInfo(ID, 4, 4) { }
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void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
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for(unsigned c = 0; c != 4; ++c)
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if (!IsColorUsedArr[c]) { // find unused color
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Node->setColor(c);
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return;
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}
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Node->getParentLR()->markForSpill();
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}
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// according to Sparc 64 ABI, all %fp CC regs are volatile
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//
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inline bool isRegVolatile(int Reg) const { return true; }
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};
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#endif
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