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ce9abb7e3a
Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
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22 lines
863 B
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid8_addr_mimg:
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vaddr
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===========================
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Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
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*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
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Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
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Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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