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4c1f3c24db
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
337 lines
14 KiB
C++
337 lines
14 KiB
C++
//===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the JIT interfaces for the ARM target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "jit"
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#include "ARMJITInfo.h"
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#include "ARM.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMRelocations.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Memory.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdlib>
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using namespace llvm;
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void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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report_fatal_error("ARMJITInfo::replaceMachineCodeForFunction");
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}
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/// JITCompilerFunction - This contains the address of the JIT function used to
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/// compile a function lazily.
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static TargetJITInfo::JITCompilerFn JITCompilerFunction;
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// Get the ASMPREFIX for the current host. This is often '_'.
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#ifndef __USER_LABEL_PREFIX__
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#define __USER_LABEL_PREFIX__
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#endif
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#define GETASMPREFIX2(X) #X
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#define GETASMPREFIX(X) GETASMPREFIX2(X)
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#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
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// CompilationCallback stub - We can't use a C function with inline assembly in
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// it, because the prolog/epilog inserted by GCC won't work for us. (We need
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// to preserve more context and manipulate the stack directly). Instead,
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// write our own wrapper, which does things our way, so we have complete
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// control over register saving and restoring.
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extern "C" {
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#if defined(__arm__)
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void ARMCompilationCallback();
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asm(
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".text\n"
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".align 2\n"
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".globl " ASMPREFIX "ARMCompilationCallback\n"
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ASMPREFIX "ARMCompilationCallback:\n"
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// Save caller saved registers since they may contain stuff
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// for the real target function right now. We have to act as if this
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// whole compilation callback doesn't exist as far as the caller is
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// concerned, so we can't just preserve the callee saved regs.
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"stmdb sp!, {r0, r1, r2, r3, lr}\n"
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#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
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"vstmdb sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
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#endif
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// The LR contains the address of the stub function on entry.
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// pass it as the argument to the C part of the callback
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"mov r0, lr\n"
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"sub sp, sp, #4\n"
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// Call the C portion of the callback
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"bl " ASMPREFIX "ARMCompilationCallbackC\n"
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"add sp, sp, #4\n"
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// Restoring the LR to the return address of the function that invoked
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// the stub and de-allocating the stack space for it requires us to
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// swap the two saved LR values on the stack, as they're backwards
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// for what we need since the pop instruction has a pre-determined
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// order for the registers.
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// +--------+
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// 0 | LR | Original return address
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// +--------+
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// 1 | LR | Stub address (start of stub)
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// 2-5 | R3..R0 | Saved registers (we need to preserve all regs)
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// 6-20 | D0..D7 | Saved VFP registers
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// +--------+
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//
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#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
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// Restore VFP caller-saved registers.
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"vldmia sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
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#endif
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//
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// We need to exchange the values in slots 0 and 1 so we can
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// return to the address in slot 1 with the address in slot 0
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// restored to the LR.
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"ldr r0, [sp,#20]\n"
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"ldr r1, [sp,#16]\n"
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"str r1, [sp,#20]\n"
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"str r0, [sp,#16]\n"
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// Return to the (newly modified) stub to invoke the real function.
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// The above twiddling of the saved return addresses allows us to
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// deallocate everything, including the LR the stub saved, with two
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// updating load instructions.
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"ldmia sp!, {r0, r1, r2, r3, lr}\n"
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"ldr pc, [sp], #4\n"
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);
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#else // Not an ARM host
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void ARMCompilationCallback() {
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llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
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}
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#endif
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}
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/// ARMCompilationCallbackC - This is the target-specific function invoked
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/// by the function stub when we did not know the real target of a call.
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/// This function must locate the start of the stub or call site and pass
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/// it into the JIT compiler function.
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extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) {
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// Get the address of the compiled code for this function.
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intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)StubAddr);
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// Rewrite the call target... so that we don't end up here every time we
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// execute the call. We're replacing the first two instructions of the
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// stub with:
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// ldr pc, [pc,#-4]
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// <addr>
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if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
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llvm_unreachable("ERROR: Unable to mark stub writable");
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}
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*(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
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*(intptr_t *)(StubAddr+4) = NewVal;
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if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
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llvm_unreachable("ERROR: Unable to mark stub executable");
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}
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}
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TargetJITInfo::LazyResolverFn
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ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) {
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JITCompilerFunction = F;
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return ARMCompilationCallback;
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}
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void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr,
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JITCodeEmitter &JCE) {
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uint8_t Buffer[4];
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uint8_t *Cur = Buffer;
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MachineCodeEmitter::emitWordLEInto(Cur, (intptr_t)Ptr);
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void *PtrAddr = JCE.allocIndirectGV(
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GV, Buffer, sizeof(Buffer), /*Alignment=*/4);
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addIndirectSymAddr(Ptr, (intptr_t)PtrAddr);
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return PtrAddr;
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}
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TargetJITInfo::StubLayout ARMJITInfo::getStubLayout() {
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// The stub contains up to 3 4-byte instructions, aligned at 4 bytes, and a
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// 4-byte address. See emitFunctionStub for details.
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StubLayout Result = {16, 4};
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return Result;
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}
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void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
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JITCodeEmitter &JCE) {
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void *Addr;
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// If this is just a call to an external function, emit a branch instead of a
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// call. The code is the same except for one bit of the last instruction.
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if (Fn != (void*)(intptr_t)ARMCompilationCallback) {
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// Branch to the corresponding function addr.
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if (IsPIC) {
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// The stub is 16-byte size and 4-aligned.
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intptr_t LazyPtr = getIndirectSymAddr(Fn);
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if (!LazyPtr) {
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// In PIC mode, the function stub is loading a lazy-ptr.
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LazyPtr= (intptr_t)emitGlobalValueIndirectSym((const GlobalValue*)F, Fn, JCE);
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DEBUG(if (F)
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errs() << "JIT: Indirect symbol emitted at [" << LazyPtr
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<< "] for GV '" << F->getName() << "'\n";
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else
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errs() << "JIT: Stub emitted at [" << LazyPtr
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<< "] for external function at '" << Fn << "'\n");
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}
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JCE.emitAlignment(4);
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Addr = (void*)JCE.getCurrentPCValue();
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if (!sys::Memory::setRangeWritable(Addr, 16)) {
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llvm_unreachable("ERROR: Unable to mark stub writable");
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}
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JCE.emitWordLE(0xe59fc004); // ldr ip, [pc, #+4]
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JCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip
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JCE.emitWordLE(0xe59cf000); // ldr pc, [ip]
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JCE.emitWordLE(LazyPtr - (intptr_t(Addr)+4+8)); // func - (L_func$scv+8)
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sys::Memory::InvalidateInstructionCache(Addr, 16);
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if (!sys::Memory::setRangeExecutable(Addr, 16)) {
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llvm_unreachable("ERROR: Unable to mark stub executable");
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}
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} else {
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// The stub is 8-byte size and 4-aligned.
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JCE.emitAlignment(4);
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Addr = (void*)JCE.getCurrentPCValue();
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if (!sys::Memory::setRangeWritable(Addr, 8)) {
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llvm_unreachable("ERROR: Unable to mark stub writable");
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}
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JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
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JCE.emitWordLE((intptr_t)Fn); // addr of function
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sys::Memory::InvalidateInstructionCache(Addr, 8);
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if (!sys::Memory::setRangeExecutable(Addr, 8)) {
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llvm_unreachable("ERROR: Unable to mark stub executable");
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}
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}
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} else {
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// The compilation callback will overwrite the first two words of this
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// stub with indirect branch instructions targeting the compiled code.
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// This stub sets the return address to restart the stub, so that
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// the new branch will be invoked when we come back.
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//
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// Branch and link to the compilation callback.
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// The stub is 16-byte size and 4-byte aligned.
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JCE.emitAlignment(4);
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Addr = (void*)JCE.getCurrentPCValue();
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if (!sys::Memory::setRangeWritable(Addr, 16)) {
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llvm_unreachable("ERROR: Unable to mark stub writable");
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}
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// Save LR so the callback can determine which stub called it.
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// The compilation callback is responsible for popping this prior
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// to returning.
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JCE.emitWordLE(0xe92d4000); // push {lr}
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// Set the return address to go back to the start of this stub.
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JCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12
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// Invoke the compilation callback.
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JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
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// The address of the compilation callback.
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JCE.emitWordLE((intptr_t)ARMCompilationCallback);
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sys::Memory::InvalidateInstructionCache(Addr, 16);
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if (!sys::Memory::setRangeExecutable(Addr, 16)) {
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llvm_unreachable("ERROR: Unable to mark stub executable");
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}
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}
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return Addr;
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}
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intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const {
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ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
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switch (RT) {
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default:
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return (intptr_t)(MR->getResultPointer());
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case ARM::reloc_arm_pic_jt:
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// Destination address - jump table base.
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return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal();
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case ARM::reloc_arm_jt_base:
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// Jump table base address.
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return getJumpTableBaseAddr(MR->getJumpTableIndex());
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case ARM::reloc_arm_cp_entry:
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case ARM::reloc_arm_vfp_cp_entry:
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// Constant pool entry address.
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return getConstantPoolEntryAddr(MR->getConstantPoolIndex());
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case ARM::reloc_arm_machine_cp_entry: {
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ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal();
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assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) &&
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"Can't handle this machine constant pool entry yet!");
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intptr_t Addr = (intptr_t)(MR->getResultPointer());
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Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment();
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return Addr;
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}
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}
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}
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/// relocate - Before the JIT can run a block of code that has been emitted,
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/// it must rewrite the code to contain the actual addresses of any
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/// referenced global symbols.
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void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
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unsigned NumRelocs, unsigned char* GOTBase) {
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for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
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void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
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intptr_t ResultPtr = resolveRelocDestAddr(MR);
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switch ((ARM::RelocationType)MR->getRelocationType()) {
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case ARM::reloc_arm_cp_entry:
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case ARM::reloc_arm_vfp_cp_entry:
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case ARM::reloc_arm_relative: {
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// It is necessary to calculate the correct PC relative value. We
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// subtract the base addr from the target addr to form a byte offset.
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ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
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// If the result is positive, set bit U(23) to 1.
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if (ResultPtr >= 0)
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*((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift;
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else {
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// Otherwise, obtain the absolute value and set bit U(23) to 0.
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*((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift);
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ResultPtr = - ResultPtr;
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}
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// Set the immed value calculated.
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// VFP immediate offset is multiplied by 4.
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if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry)
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ResultPtr = ResultPtr >> 2;
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*((intptr_t*)RelocPos) |= ResultPtr;
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// Set register Rn to PC (which is register 15 on all architectures).
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// FIXME: This avoids the need for register info in the JIT class.
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*((intptr_t*)RelocPos) |= 15 << ARMII::RegRnShift;
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break;
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}
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case ARM::reloc_arm_pic_jt:
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case ARM::reloc_arm_machine_cp_entry:
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case ARM::reloc_arm_absolute: {
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// These addresses have already been resolved.
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*((intptr_t*)RelocPos) |= (intptr_t)ResultPtr;
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break;
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}
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case ARM::reloc_arm_branch: {
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// It is necessary to calculate the correct value of signed_immed_24
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// field. We subtract the base addr from the target addr to form a
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// byte offset, which must be inside the range -33554432 and +33554428.
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// Then, we set the signed_immed_24 field of the instruction to bits
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// [25:2] of the byte offset. More details ARM-ARM p. A4-11.
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ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
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ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2;
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assert(ResultPtr >= -33554432 && ResultPtr <= 33554428);
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*((intptr_t*)RelocPos) |= ResultPtr;
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break;
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}
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case ARM::reloc_arm_jt_base: {
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// JT base - (instruction addr + 8)
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ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
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*((intptr_t*)RelocPos) |= ResultPtr;
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break;
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}
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case ARM::reloc_arm_movw: {
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ResultPtr = ResultPtr & 0xFFFF;
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*((intptr_t*)RelocPos) |= ResultPtr & 0xFFF;
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*((intptr_t*)RelocPos) |= ((ResultPtr >> 12) & 0xF) << 16;
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break;
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}
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case ARM::reloc_arm_movt: {
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ResultPtr = (ResultPtr >> 16) & 0xFFFF;
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*((intptr_t*)RelocPos) |= ResultPtr & 0xFFF;
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*((intptr_t*)RelocPos) |= ((ResultPtr >> 12) & 0xF) << 16;
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break;
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}
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}
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}
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}
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