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4c1f3c24db
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
126 lines
4.2 KiB
C++
126 lines
4.2 KiB
C++
//===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower ARM MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMAsmPrinter.h"
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#include "MCTargetDesc/ARMMCExpr.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
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const MCSymbol *Symbol) {
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const MCExpr *Expr;
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switch (MO.getTargetFlags()) {
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default: {
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Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
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OutContext);
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switch (MO.getTargetFlags()) {
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default: llvm_unreachable("Unknown target flag on symbol operand");
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case 0:
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break;
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case ARMII::MO_LO16:
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Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
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OutContext);
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Expr = ARMMCExpr::CreateLower16(Expr, OutContext);
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break;
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case ARMII::MO_HI16:
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Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
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OutContext);
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Expr = ARMMCExpr::CreateUpper16(Expr, OutContext);
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break;
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}
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break;
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}
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case ARMII::MO_PLT:
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Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT,
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OutContext);
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break;
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}
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if (!MO.isJTI() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(Expr,
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MCConstantExpr::Create(MO.getOffset(),
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OutContext),
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OutContext);
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return MCOperand::CreateExpr(Expr);
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}
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bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) {
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switch (MO.getType()) {
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default: llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all non-CPSR implicit register operands.
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if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
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return false;
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
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MO.getMBB()->getSymbol(), OutContext));
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = GetSymbolRef(MO, Mang->getSymbol(MO.getGlobal()));
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = GetSymbolRef(MO,
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GetExternalSymbolSymbol(MO.getSymbolName()));
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
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break;
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case MachineOperand::MO_FPImmediate: {
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APFloat Val = MO.getFPImm()->getValueAPF();
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bool ignored;
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Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored);
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MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
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break;
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}
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case MachineOperand::MO_RegisterMask:
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// Ignore call clobbers.
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return false;
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}
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return true;
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}
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void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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ARMAsmPrinter &AP) {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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if (AP.lowerOperand(MO, MCOp))
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OutMI.addOperand(MCOp);
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}
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}
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