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110 lines
5.5 KiB
TableGen
110 lines
5.5 KiB
TableGen
//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G5 (970) processor.
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//
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//===----------------------------------------------------------------------===//
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def G5Itineraries : ProcessorItineraries<
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[IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [
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InstrItinData<IntSimple , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>,
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InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>,
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InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>,
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InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>,
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InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>,
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InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
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InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
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InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>,
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InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>,
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InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>,
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InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IntRotateDI , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>,
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InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IntTrapW , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
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InstrItinData<BrCR , [InstrStage<4, [BPU]>]>,
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InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>,
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InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>,
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InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>,
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InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>,
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InstrItinData<LdStSTFD , [InstrStage<4, [SLU]>]>,
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InstrItinData<LdStSTFDU , [InstrStage<4, [SLU]>]>,
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InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>,
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InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>,
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InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>,
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InstrItinData<LdStLHAU , [InstrStage<5, [SLU]>]>,
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InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>,
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InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>,
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InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>,
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InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
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InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>,
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InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>,
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InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>,
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InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
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InstrItinData<SprISYNC , [InstrStage<40, [SLU]>]>, // needs work
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InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>,
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InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>,
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InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>,
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InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>,
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InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>,
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InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>,
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InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>,
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InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>,
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InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>,
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InstrItinData<SprSC , [InstrStage<1, [IU2]>]>,
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InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
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InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>,
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InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>,
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InstrItinData<FPFused , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<FPRes , [InstrStage<6, [FPU1, FPU2]>]>,
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InstrItinData<FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>,
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InstrItinData<VecGeneral , [InstrStage<2, [VIU1]>]>,
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InstrItinData<VecFP , [InstrStage<8, [VFPU]>]>,
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InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
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InstrItinData<VecComplex , [InstrStage<5, [VIU2]>]>,
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InstrItinData<VecPerm , [InstrStage<3, [VPU]>]>,
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InstrItinData<VecFPRound , [InstrStage<8, [VFPU]>]>,
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InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>,
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InstrItinData<VecVSR , [InstrStage<3, [VPU]>]>
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]>;
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// ===---------------------------------------------------------------------===//
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// e5500 machine model for scheduling and other instruction cost heuristics.
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def G5Model : SchedMachineModel {
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let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
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let MinLatency = 0; // Out-of-order dispatch.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 16;
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let Itineraries = G5Itineraries;
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}
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